Chapter 8. Capacity upgrades 219
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm
򐂰zSeries Application Assist Processors (zAAPs), which are designed to operate
asynchronously with the CPs to execute Java programming under control of IBM Java
Virtual Machine (JVM) for logical partitions running z/OS. The IBM JVM processing cycles
can be executed on the configured zAAPs with no anticipated modifications to the Java
applications.
򐂰IEEE Floating Point: used by Java and C/C++ applications, the new Binary Floating Point
unit halves the number of cycles required on previous servers.
򐂰Secondary level Translation Lookaside Buffer (TLB): a secondary cache for Dynamic
Address Translation, for both the instruction and data caches, increases the number of
buffer entries by a factor of eight.
򐂰CP Assist for Cryptographic Function (CPACF): implemented on each PU, the assist
function uses five new instructions for symmetrical clear key cryptographic encryption and
encryption operations, to accelerate the encryption and decryption of SSL transactions,
and VPN encrypted data transfers.
In addition, the following improvements for specific areas are also implemented on z990:
򐂰Compression Unit:
The Compression Unit is integrated with the CP Assist for Cryptographic Function,
benefiting from combining the use of buffers and interfaces. It is implemented on each PU
and provides excellent hardware compression performance.
򐂰Checksum offload for IPV4 packets when in QDIO mode for Linux and z/OS:
Checksum Offload provides the capability of calculating the Transmission Control Protocol
(TCP), User Datagram Protocol (UDP), and Internet Protocol (IP) header checksums.
Checksum verifies the correctness of files. By moving the checksum calculations to a
Gigabit or 1000BASE-T Ethernet feature, host CPU cycles are reduced and performance
is improved. It is supported by the OSA-Express GbE and 1000BASE-T Ethernet features
when operating at 1 Gbps.
Multi-book structure
The multiple book structure introduced with the z990 servers offers more flexibility, capacity
and scalability to the system.
Each book has its own MCM (which contains PUs and L2 cache), memory cards, and MBAs
with their STIs. Up to four books are connected through L2 caches by concentric rings,
resulting in a single integrated system.
Previous zSeries servers have PU clusters, or PU sets, which are also connected to each
other through L2 caches. But in those cases all PUs and L2 caches reside in a single MCM.
The z990 multi-MCM design introduces two types of PU to L2 cache access: a “local” access,
when the PU and L2 cache are located in the same MCM (or book), and a “remote” access,
when PU and L2 cache are located in different books.
Figure 8-16 shows a two-book z990 server logical view.