6947ch02.fm

Draft Document for Review April 7, 2004 6:15 pm

and SOAP technologies are used. The High Level Assembler will be the first to support the Extended Translation Facility instructions.

2.2.4 Processor unit functions

One of the key components of the z990 server is the processor unit (PU). This is the microprocessor chip where instructions are executed and the related data resides. The instructions and the data are stored in the PU’s high-speed buffer, called the Level 1 cache. Each PU has its own 512 KB Level 1 cache, split into 256 KB for data and 256 KB for instructions.

The L1 cache is designed as a store-through cache, which means that altered data is synchronously stored into the next level, the L2 cache. Each PU has multiple processors inside and instructions are executed twice, asynchronously, on both processors.

This asymmetric mirroring of instruction execution runs one cycle behind the actual operation. This allows the circuitry on the chip to be optimized for performance and does not compromise the simplified error detection process that is inherent to a mirrored execution unit design.

One or two processor units are contained on one processor chip. All PUs of a z990 server reside in a MultiChip Module. An MCM holds 12 PUs, of which eight are available for customer use, two are SAPs and two are spares. Up to four MCMs, each contained in a book, may be available in one z990 server.

This approach allows a z990 server to have more PUs than required for a given initial configuration. This is a key point of the z990 design and is the foundation for the configuration flexibility and scalability of a single server.

All PUs in a z990 server are physically identical, but at initialization time PUs can be characterized to specific functions: CP, IFL, ICF, zAAP or SAP. The function assigned to a PU is set by the Licensed Internal Code loaded when the system is initialized (Power-on Reset) and the PU is “characterized”. Only characterized PUs have a designated function; non-characterized PUs are considered spares.

This design brings an outstanding flexibility to the z990 server, as any PU can assume any available characterization. This also plays an essential role in z990 system availability, as these PU assignments can be done dynamically, with no server outage, allowing:

￿Concurrent upgrades

Except on a fully configured model, concurrent upgrades can be done by the Licensed Internal Code, which assigns a PU function to a previously non-characterized PU. Within the book boundary or boundary of multiple books, no hardware changes are required and the upgrade can be done via Capacity Upgrade on Demand (CUoD), Customer Initiated Upgrade (CIU), On/Off Capacity on Demand (On/Off CoD), or Capacity BackUp (CBU). More information about capacity upgrades is provided in “Concurrent upgrades” on page 186.

￿PU sparing

In the rare case of a PU failure, the failed PU’s characterization is dynamically and transparently reassigned to a spare PU. More information on PU sparing is provided in “Sparing rules” on page 52.

A minimum of one PU per z990 server must be ordered as one of the following:

￿A Central processor (CP)

￿An Integrated Facility for Linux (IFL)

46IBM eServer zSeries 990 Technical Guide

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IBM 990 manual Processor unit functions
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990 specifications

The IBM 990 series, often referred to in the context of IBM's pioneering efforts in the realm of mainframe computing, represents a unique chapter in the history of information technology. Introduced in the late 1960s, the IBM 990 series was designed as a powerful tool for enterprise-level data processing and scientific calculations, showcasing the company's commitment to advancing computing capabilities.

One of the main features of the IBM 990 was its architecture, which was built to support a wide range of applications, from business processing to complex scientific computations. The system employed a 32-bit word length, which was advanced for its time, allowing for more flexible and efficient data handling. CPUs in the IBM 990 series supported multiple instructions per cycle, which contributed significantly to the overall efficiency and processing power of the machines.

The technology behind the IBM 990 was also notable for its use of solid-state technology. This provided a shift away from vacuum tube systems that were prevalent in earlier computing systems, enhancing the reliability and longevity of the hardware. The IBM 990 series utilized core memory, which was faster and more reliable than the magnetic drum memory systems that had been standard up to that point.

Another defining characteristic of the IBM 990 was its extensibility. Organizations could configure the machine to suit their specific needs by adding memory, storage, and peripheral devices as required. This modular approach facilitated the growth of systems alongside the technological and operational demands of the business environments they served.

In terms of software, the IBM 990 series was compatible with a variety of operating systems and programming environments, including FORTRAN and COBOL, enabling users to access a broader array of applications. This versatility was a significant advantage, making the IBM 990 an appealing choice for educational institutions, research facilities, and enterprises alike.

Moreover, the IBM 990 was engineered to support multiprocessing, which allowed multiple processes to run simultaneously, further increasing its effectiveness in tackling complex computing tasks.

In summary, the IBM 990 series represents a significant advancement in computing technology during the late 20th century. With a robust architecture, versatile configuration options, and a focus on solid-state technology, the IBM 990 facilitated substantial improvements in data processing capabilities, making it a cornerstone for many businesses and academic institutions of its time. Its impact can still be seen today in the continued evolution of mainframe computing.
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