Chapter 2. System structure and design 37
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm

The dual-core PU chips share the path to the SC chip (L2 control) and the clock chip (CLK).

2.1.9 Summary

Table2-2 summarizes all aspects of the z990 system structure.

Table 2-2 System structure summary
2.2 System design

The IBM z990 Symmetrical Multi Processor (SMP) design is the next step in an evolutionary

trajectory stemming from the introduction of CMOS technology back in 1994. Over time the

IBM 2084-A08 IBM 2084-B16 IBM 2 084-C24 IBM 2084-D 32
Number of MCMs1234
Total number of PUs12243648
Maximum number of
characterized PUs 8 162432
Number of CPs 0 - 8 0 - 16 0 - 24 0 - 32
Number of IFLs 0 - 8 0 - 16 0 - 24 0 - 32
Number of ICFs 0 - 8 0 - 16 0 - 16 0 - 16
Number of zAAPs 0 - 4 0 - 8 0 - 12 0- 16
Standard SAPs 2468
Standard spare PUs2468
Number of memory
cards 2468
Enabled Memory
Sizes (multiples of 8
GB)
16 - 64 GB 16 - 128 GB 16 - 192 GB 16 - 256 GB
L1 Cache per PU 256/256 KB 256/256 KB 256/256 KB 256/256 KB
L2 Cache 32 MB 64 MB 96 MB 128 MB
Cycle time (ns) 0.83 0.83 0.83 0.83
Maximum number of
STIs 12 24 36 48
STI bandwidth/STI 2.0 GB/sec 2.0 GB/sec 2.0 GB/sec 2.0 GB/sec
Max STI bandwidth 24 GB/sec 48 GB/sec 72 GB/sec 96 GB/sec
Maximum number of
I/O cages 3333
Number of Support
Elements 2222
External power 3 phase 3 phase 3 phase 3 phase
Internal Battery
Feature optional optional optional optional