6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm
24 IBM eServer zSeries 990 Technical Guide
2.1 System structure
The z990 structure and design are the result of the continuous evolution of S/390 and zSeries
since CMOS servers were introduced in 1994. The structure and design have been
continuously improved, adding more capacity, performance, functionality, and connectivity.
The objective of z990 system structure and design is to offer a flexible infrastructure to
accommodate a wide range of operating systems and applications, whether they be
traditional or emerging e-business applications based on WebSphere, Java, and Linux, for
integration and deployment in heterogeneous business solutions.
For that purpose, the z990 introduces a superscalar microprocessor architecture, improving
uniprocessor performance and providing an increase in the number of usable processors per
system. In order to keep a balanced system, the I/O bandwidth and available memory sizes
have been increased accordingly.

2.1.1 Book concept

The z990 Central Processor Complex (CPC) introduces a packaging concept based on
books. A book contains processors (PUs), memory, and connectors to I/O cages and ICB-4
links. Books are located in the CEC cage in Frame A. A z990 server (CPC) has at least one
book, but may have up to four books installed.
A book and its components is shown in Figure2-1. Each book contains:
򐂰12 processor units (PUs). The PUs reside on microprocessor chips located on a
Multi-Chip Module (MCM).
򐂰16 GB to 64 GB physical memory. There are always two memory cards, each containing
8, 16, or 32 GB.
򐂰Three Memory Bus Adapters (MBAs), supporting up to 12 Self-Timed Interconnects
(STIs) to the I/O cages and/or ICB-4 channels.
Figure 2-1 Book structure and components
Up to four books can reside in the CEC cage. Books plug into cards, which plug into slots of
the CEC cage board.
STI Slots
MCM
Memory cards