6947ch08.fm

Draft Document for Review April 7, 2004 6:15 pm

 

Book 0

 

 

Book 1

 

PU

 

PU

PU

 

PU

L1

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L1

L1

...

L1

 

 

 

 

 

Ring

 

 

 

L2 Cache

 

Structure

L2 Cache

 

 

 

 

 

Memory

 

Memory

 

 

 

MBA

 

 

MBA

Figure 8-16 Two-book system logical view

In this example, a local access is done by the first PU on Book 0 to its local L2 cache, and a remote access is done by the last PU on Book 1 to the L2 cache on Book 1. As the access time of the remote connection is higher than a local one, the performance of such a system would not be as consistent as a single MCM system, being dependent on the remote access rates. To avoid this effect, z990 has implemented some optimizations.

The L2 cache is implemented as a processor cache, not as a memory cache. This means that data (and instructions) are normally residents in the L2 cache on the book where it is being used by a PU, and not in the book where the associated memory address resides. So in the previous example, the L2 cache in Book 1 will have the data/instructions used by its local PU after the remote L2 cache access.

Along with the PU allocation and assignment algorithm during IML, described in “Processor unit characterization” on page 51, the PR/SM has a major role in the z990 system optimization.

The z990 PR/SM has changed to support the multi-book structure and to provide optimal system performance. PR/SM is aware of the physical book structure, while the logical partitions do not require awareness about this design. The PR/SM hypervisor manages and optimizes allocation and dispatching for the underlying physical topology, providing a transparent multi-book implementation to operating systems. The PR/SM main objective is to allocate all processors and storage for a logical partition to the same book, and to redispatch a logical processor back to the same physical processor.

This implementation provides optimal performance and a more linear scalability to the z990 server. The results can be observed in the LSPR’s ITR values from the uniprocessor to the 32-way server.

8.7.2 Superscalar processors

The z990 server is the first generation of zSeries servers that uses superscalar processors. A superscalar processor can execute multiple instructions per cycle, potentially providing better performance than a sequential processor running at the same cycle time (or processor frequency).

220IBM eServer zSeries 990 Technical Guide

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IBM 990 manual Book, Superscalar processors
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990 specifications

The IBM 990 series, often referred to in the context of IBM's pioneering efforts in the realm of mainframe computing, represents a unique chapter in the history of information technology. Introduced in the late 1960s, the IBM 990 series was designed as a powerful tool for enterprise-level data processing and scientific calculations, showcasing the company's commitment to advancing computing capabilities.

One of the main features of the IBM 990 was its architecture, which was built to support a wide range of applications, from business processing to complex scientific computations. The system employed a 32-bit word length, which was advanced for its time, allowing for more flexible and efficient data handling. CPUs in the IBM 990 series supported multiple instructions per cycle, which contributed significantly to the overall efficiency and processing power of the machines.

The technology behind the IBM 990 was also notable for its use of solid-state technology. This provided a shift away from vacuum tube systems that were prevalent in earlier computing systems, enhancing the reliability and longevity of the hardware. The IBM 990 series utilized core memory, which was faster and more reliable than the magnetic drum memory systems that had been standard up to that point.

Another defining characteristic of the IBM 990 was its extensibility. Organizations could configure the machine to suit their specific needs by adding memory, storage, and peripheral devices as required. This modular approach facilitated the growth of systems alongside the technological and operational demands of the business environments they served.

In terms of software, the IBM 990 series was compatible with a variety of operating systems and programming environments, including FORTRAN and COBOL, enabling users to access a broader array of applications. This versatility was a significant advantage, making the IBM 990 an appealing choice for educational institutions, research facilities, and enterprises alike.

Moreover, the IBM 990 was engineered to support multiprocessing, which allowed multiple processes to run simultaneously, further increasing its effectiveness in tackling complex computing tasks.

In summary, the IBM 990 series represents a significant advancement in computing technology during the late 20th century. With a robust architecture, versatile configuration options, and a focus on solid-state technology, the IBM 990 facilitated substantial improvements in data processing capabilities, making it a cornerstone for many businesses and academic institutions of its time. Its impact can still be seen today in the continued evolution of mainframe computing.
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