Intel 31244 PCI-X manual Trace Impedance, Differential Impedance

Models: 31244 PCI-X

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4.5Trace Impedance

All signal layers require controlled impedance of 50 +/- 15%, microstrip or stripline where appropriate, unless otherwise specified. Selecting the appropriate board stack-up to minimize impedance variations is very important. When calculating flight times, it is important to consider the minimum and maximum trace impedance based on the switching neighboring traces. Use wider spaces between traces, since this may minimize trace-to-trace coupling, and reduce cross talk.

All recommendations described in this document assume a Twid 5 mil 50 signal trace, unless otherwise specified. When a different stack up is used the trace widths must be adjusted appropriately. When wider traces are used, the trace spacing must be adjusted accordingly (linearly).

It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The following Impedance Calculator URLs provide approximations for the trace impedance of various topologies. They may be used to generate the starting point for a full 2D Field solver.

http://emclab.umr.edu/pcbtlc/

http://www.westak.com/techcenter/imped/

The following website link provides a useful basic guideline for calculating trace parameters:

http://www.ultracad.com/calc.htm

Note: Using stripline transmission lines may give better results than microstrip. This is due to the difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in limiting the plated thickness of microstrip conductors, which may substantially increase cross-talk.

4.5.1Differential Impedance

The Serial ATA standard defines a 100 ohms differential impedance. This section provides some basic background information on the differential impedance calculations. In the cross section of Figure 9 shows the cross section of two traces of a differential pair.

Figure 9. Cross Section of Differential Trace

Ground reference plane

To calculate the coupled impedance requires a 2x2 matrix. The diagonal values in the matrix represent the impedance of the traces to ground and the off-diagonal values provide a measure of how tightly the traces are coupled. The differential impedance is the value of the line-to-line resistor terminator that optimally terminates pure differential signals. The two by two matrix is shown below as:

Example 1. Two-by-two Differential Impedance Matrix

Zo =

Z11 Z12 Z21 Z22

Design Guide

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Intel 31244 PCI-X manual Trace Impedance, Example 1. Two-by-two Differential Impedance Matrix