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Intel 31244 PCI-X 6.1 Intel 31244 PCI-X to Serial ATA Controller Normal Mode (standard SATA driver)

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38 Design Guide

Intel® 31244 PCI-X to Serial ATA Controller

Printed Circuit Board (PCB) Methodology

6.1 Intel® 31244 PCI-X to Serial ATA ControllerNormal Mode (standard SATA driver)

This section provides recommendations for the GD31244 running in the standard SATA mode.

Figure 11 shows a standard SATA setup with the GD31244 connected to trace on the motherboard.

This trace terminates with a connector. The SATA cable connects to the SA TA motherboard cable

with the other end connecting to connecto r on the hard drive. The traces from the SATA ha rd drive

connector connect to the SATA interface IC on the hard drive.

Figure 11. Inte l® 31244 PCI-X to Serial ATA Controller Connection Scheme - Normal Mode

Table 11. Normal Voltage Mode

Parameter Routing Guid eline

Single Ended Trace Impedance Microstrip stackup

Reference Plane ground

Impedance 100 ohms differential impe da nc e

Trace Thickness 1.4 mil

Trace Width 5 mil

Intra Pair Trace Spacing 7 mil

Pair to Pair

Trace Spacing 20 mil minimum

Trace Length 2” to 5”

Trace Length Matching 100 mils

Cable Length 1 meter

Hard drive PCB Length from co nnector to SATA

interface IC. 1”

Vias Minimize number of vias (n one preferred). Each

channel in the pair has an equal number of vias.

B0423-02

Cable

Conn.

HD

Traces

Conn.

MB

Traces

Intel®

31244 SATA IC

Contents

Main Intel 31244 PCI-X to Serial ATA Controller Contents Page Figures Tables Contents Revision History Page About This Document 1 1.1 Reference Documentation 1.2 Terminology and Definitions For the latest revision and documentation number , con tac t your Intel representative. Table 1. Reference Documents About This Document Table 2. Terminology and Definition (Sheet 2 of 3) About This Document Table 2. Terminology and Definition (She et 3 of 3) Page Overview 2 2.1 Features I/O Reads I/O Writes Single Memory Reads Multiple Memory Reads Overview Feature Highlights: Figure 1. Intel 31244 PCI-X to Serial ATA Controller Block Diagram Dual Port FIFO and I/O Transport Engine PCI-X 64-bit 133 MHz Interface 2.2 Applications JTAG Intel 31244 PCI-X to Serial ATA Controller PCI-X Bus Port 0 Page Intel 31244 PCI-X to Serial ATA Controller Package 3 3.1 Signal Pin Descriptions Table 4. PCI-X Bus Pin Descriptions (Sheet 1 of 2) Table 5. Configuration Pin Descriptions Table 6. JTAG Pin Descriptions Table 4. PCI-X Bus Pin Descriptions (Sheet 2 of 2) 3.1.1 VA0, VA1 (VCCPLL) Pin Requirements Table 7. Serial ROM Interface Pin Descriptions Table 8. Power Supply Pin Desc r iptions This page left intentionally blank. 3.2 Package/Marking Information Date Code 31244 XX Intel 3.3 Ball Map By Function B0419-02 PCI-X Interface Pins SERDES section VIO 3.3V VSS VCC is 2.5V JTAG Section Page Routing Guidelines 4 4.1 General Routing Guidelines power distribution minimizing crosstalk 4.2 Crosstalk 4.3 EMI Considerations 4.4 Power Distribution and Decoupl ing 4.4.1 Decoupling 4.4.1.1 Intel 31244 PCI-X to Serial ATA Controller Decoupling 4.5 Trace Impedance 4.5.1 Differential Impedance Page Intel 31244 PCI-X to Serial ATA Controller Interface Ports 5 5.1 Serial ROM Interface 5.2 JTAG Interface 5.3 PCI-X Interface I/O Reads I/O Writes Single Memory Reads Multiple Memory Reads 5.4 Serial ATA Interface 5.4.1 Direct Port Access (DPA) 5.4.2 Extended Voltage Mode 5.4.3 LED Interface 5.4.4 Reference Clock Generation Page Printed Circuit Board (PCB) Methodology 6 backplane cables motherboard connectors 6.1 Intel 31244 PCI-X to Serial ATA Controller Normal Mode (standard SATA driver) Conn. 6.1.1 Intel 31244 PCI-X to Serial ATA Controller HBA Stackup 6.2 Extended Voltage Mode 6.2.1 Backplane Topologies Printed Circuit Board (PCB) Methodology Figure 14. Read Ba ckplane Topology a. Read Backplane Topology b. Read Backplane with Cable Topology 6.2.2 Motherboard Stackup for Backplane Designs Figure 15. Microstrip Stackup +-+- Er = 4.15 6.2.3 Backplane Stripline Stackup 6.2.4 Cable Interconnect With Backplane Page PCI-X Layout Guidelines 7 7.1 PCI Voltage Levels 7.2 PCI/X Clocking Modes 7.3 PCI General Layout Guidelines 7.4 PCI-X Layout Guidelines For Slot Configurations 7.4.1 Protection Circuitry for Add-in Cards 7.4.2 PCI Clock Layout Guidelines 7.4.3 Connecting Intel 31244 PCI-X to Serial ATA Controller to Single-Slot 7.4.4 Embedded Intel 31244 PCI-X to Serial ATA Controller Single PCI-X Load 7.4.5 Embedded Intel 31244 PCI-X to Serial ATA Controller Design With Multiple PCI-X Loads Cables and Connectors 8 8.1 Cabling Page Page 8.1.1 Serial ATA Cable Voltage Power Delivery 9 9.1 Intel 31244 PCI-X to Serial ATA Controller Core Supply Voltage: Providing 2.5 V in 3.3 V System Page Test Methodology 10 Page 10.1 Extended Volt age Mode 10.1.1 Extended Voltage Mode Receiver Model 10.1.2 Extended Voltage Mode Driver Model Terminations: Pull-down/Pull-ups 11 Terminations: Pull-down/P ull - ups Table 30. Terminations: Pull-up/Pull-down (Sheet 2 of 2) Intel IQ31244 PCI-X to Serial ATA Controller Evaluation Platform Board Intel IQ31244 PCI-X to Serial ATA Controller Evaluation Platform Board 12 Intel PCI-X Expansion Slot 80321 I/O Processor 12.1 Features Debug Connectors and Logic Analyzer Connectivity 13 13.1 Probing PCI- X Signals Debug Connectors and Logic Analyzer Connectivity Table 32. Logic Analyzer Pod 2 Table 31. Logic Analyzer Pod 1 (She et 2 of 2) Table 33. Logic Analyzer Pod 3 Debug Connectors and Logic Analyzer Connectivity Table 34. Logic Analyzer Pod 4 Table 35. Logic Analyzer Pod 5 Page Page Page Page Thermal Solutions 15 15.1 Thermal Recommendations Page References 16 16.1 Related Documents