Intel® 31244 PCI-X to Serial ATA Controller
7.4.3Connecting Intel® 31244
Figure 17 shows one of the chipset PCI AD lines connected through W1 and W12 line segments, to a single-slot connector through W13 line segment, to the GD31244. This AD line is also used as an IDSEL line from line segment W14 to a 2K resistor through W15 to the PCI connector. The other end of the PCI connector IDSEL line connects through W16 to GD31244 IDSEL line input buffer. Table 22 shows the wiring lengths for a single slot design. This design layout wiring lengths should support PCI-X speeds. However, prelayout simulation is recommended.
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Figure 17. Single-Slot Topology
W1 2 W11
1 | 10 |
Host
W12 12
11
W14 2K W15
W13
1314
Slot 1
W16
15 16
17
1819
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| • Stublengths are represented by W#s |
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Table 22. | Wiring Lengths for Single Slot |
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| Segment | Lower AD Bus | Upper AD Bus | Units | ||
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| Minimum Length | Maximum Length | Minimum Length | Maximum Length |
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| W1 | 2.0 | 8 | 2 | 7 | inches |
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| W12 | 0.1 | 0.5 | 0.1 | 0.5 | inches |
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| W13 | 0.75 | 1.5 | 1.75 | 2.75 | inches |
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| W14 | 0.1 | Note | N/A | N/A | inches |
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| W15 | Note | 0.6 | N/A | N/A | inches |
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| W16 | 1.125 | 1.125 | N/A | N/A | inches |
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Note: W14, W15 and W16 represent the IDSEL line. W14 and W15 <= 0.8”.
52 | Design Guide |
