Intel IXP2800 3.5 Branch Target Buffer (BTB)

94 Hardware Reference Manual
Intel® IXP2800 Network Processor
Intel XScale® Core
Example 20 shows how a routine, called “lockMe” in this example, might be locked into the
instruction cache. Note that it is possible to receive an exception while locking code.
3.4.2.5 Unlocking Instructions in the Instruction Cache
The Intel XScale® core provides a global unlock command for the instruction cache. Writing to
coprocessor1 5, register 9 unlocks all the locked lines in the instruction cache and leaves them
valid. These lines then become available for the round-robin replacement algorithm.
3.5 Branch Target Buffer (BTB)
The Intel XScale® core uses dynamic branch prediction to reduce the penalties associated with
changing the flow of program execution. The Intel XScale® core features a branch target buffer
that provides the instruction cache with the target address of branch type instructions. The branch
target buffer is implemented as a 128-entry, direct mapped cache.
3.5.1 Branch Target Buffer Operation
The BTB stores the history of branches that have executed along with their targets. Figure20
shows an entry in the BTB, where the tag is the instruction address of a previously executed branch
and the data contains the target address of the previously executed branch along with two bits of
history information.
Example 20. Locking Code into the Cache
lockMe: ; This is the code that will be locked into the cache
mov r0, #5
add r5, r1, r2
. . .
lockMeEnd:
. . .
codeLock: ; here is the code to lock the “lockMe” routine
ldr r0, =(lockMe AND NOT 31); r0 gets a pointer to the first line we
should lock
ldr r1, =(lockMeEnd AND NOT 31); r1 contains a pointer to the last line we
should lock
lockLoop:
mcr p15, 0, r0, c9, c1, 0; lock next line of code into ICache
cmp r0, r1 ; are we done yet?
add r0, r0, #32 ; advance pointer to next line
bne lockLoop ; if not done, do the next line