Intel MPCBL0001 manual PCI Mapping for Hardware Component Subsystem, 0XFF

Intel NetStructure® MPCBL0001 High Performance Single Board Computer

Contents

Table 8 shows the PCI mapping of the component subsystem of the baseboard.

Table 8.	PCI Mapping for Hardware Component Subsystem
	Bus	Device	Function	Hardware Component Subsystem
	0	0	0	E7501 MCH Bridge
	0	0	1	MCH <-> ICH3
	0	2	0	82870P2 PCI-X Bridge (PMC and Gigabit Ethernet Controller)
	0	3	0	MCH <-> 82870P2 PCI-X Bridge (Fibre Channel Controller)
	0	29	0	USB Controller
	0	31	1	IDE Interface (hard disk drive)
	0	31	3	IPMC Interface
	2	29	0	PCI-X Bridge to Gigabit Ethernet Controller
	2	1	0	PCI-X Bridge to PMC Card
	3	1	0	PMC Card
	4	1	0	Gigabit Ethernet Controller (Port A)
	4	29	1	Gigabit Ethernet Controller (Port A)
	5	29	0	PCI-X Bridge to Fibre Channel Controller
	7	1	0	Fibre Channel Controller (Port A)
	7	1	1	Fibre Channel Controller (Port B)
	0XFF	-	-	PSB (processor-side bus) Error

NOTE: This table is for MPCBL0001F04 boards. Bus Devices 5 and 7 do not exist for MPCBL0001N04 boards.

Example:

To decode the device and function number from the System Event Log, refer to the following method.

0144 05/26/04 15:24:42 4023 13 Critical Interrupt 07 PCI PERR 6f [a4 04 08]

•Event data 1 = a4

Comments: FromTable 3 on page 33, event data 1, bit 3:0 is referring to PCI-PERR

•Event data 2 = 04.

Comments: From Table 3, event data 2, bit 7:0 is referring to Bus number 4.

•Event data 3 = 08 = 00001000

Comments: FromTable 3, event data 3, bit 7:3 is equivalent to 1 which refers to Device number 1. Event data 3, bit 2:0 is equivalent to 0 which refers to Function number 0. From Table 8 above, the PCI parity error was on the interface of the Gigabit Ethernet Controller (Port A).

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