Intel MPCBL0001 manual Processor Events, Dimm Memory Events, System Firmware Progress Post Error

Intel NetStructure® MPCBL0001 High Performance Single Board Computer

Contents

3.2.2Processor Events

The processor asserts IERR as the result of an internal error. A thermal trip error indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Upon THERMTRIP assertion, the IPMC powers down the boards.

3.2.3DIMM Memory Events

The MCH (E7501) instructs the ICH3 to report memory parity errors via SMI#. The SMI handler extracts the error information (address) from the DRAM error registers in the MCH and logs it into the SEL. The KCS interface performs error reporting to IPMC. BIOS sends a platform event message with the appropriate data to the IPMC, which logs the event to SEL and forwards the event to the Shelf Manager. Correctable memory errors generate an SMI and are logged into SEL. Normally, a board with non-correctable errors is likely to hang as the multi-bit error may cause the CPU to execute corrupted instructions. If the CPU executes corrupted instructions before executing the code to log the event, then this event will not be logged in the SEL.

3.2.4System Firmware Progress (POST Error)

The BIOS is able to log both POST and critical events to the IPMC error log. (Refer to Table 89, “BIOS Error Messages” on page 138.)

3.2.5Critical Interrupts

In general, the system BIOS is capable of generating requests on the KCS interface to communicate with the IPMC for error logging, fault resilience, critical interrupts and reading/ writing inventory CPUs and RAM information to the IPMC. Two LPC interfaces are available for the BIOS to communicate to the IPMC. The BIOS uses the SMS interface for normal communication with the IPMC and the SMM interface when executing code under SMM mode.

PCI errors implemented in the MPCBL0001 are handled as follows:

1.The MCH(E7501) sends a parity error/system error (PERR/SERR) message over the hub interface to the ICH3 notifying it that an error occurred.

2.The ICH3 generates an SMI# interrupt when it receives a PERR/SERR message.

3.The SMI handler checks the error status registers of CPU/MCH until it identifies the source and type of the error.

4.The handler sends a message to the IPMC via the KCS interface, causing it to log the error in the IPMC’s event log. IPMC then forwards the event to Shelf Manager to log it into Shelf Manager SEL.

Technical Product Specification	41
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