Intel MPCBL0001 manual Cold Boot, Power Good, Reset Actions System Function Memory Status

Intel NetStructure® MPCBL0001 High Performance Single Board Computer

Contents

3.12.5Cold Boot

Any soft reset that does not meet the configuration described in the preceding Warm Boot section is classified as a cold boot. Execution starts at the reset vector, and BIOS initializes and configures all devices, including memory subsystem, as if a hard reset had occurred. See Table 25, “Reset Actions” on page 61.

During a cold boot the BIOS initializes the warm reset counter to 0x0A and clears the reset flag to 1234h. Software can then read the reset flag to determine the type of reset.

Table 25.	Reset Actions
	Reset Actions	System Function	Memory Status
	Warm boot	Partial restart	Preserves memory above 8MB boundary
	Cold boot	Full restart	Functionally equivalent to a hard reset.

3.12.6Power Good

When the MPCBL0001 SBC is inserted into the chassis, the hardware management circuitry is “hot plugged.” The hardware management voltage is immediately applied, and the on-board IPMC is reset. After the hardware management reset, the operation of the IPMC and full power-up of the SBC are under firmware control.

Upon command to power on the module, the IPMC asserts the “power enable” signal to the on- board DC/DC converters. Full power-up of the SBC is sequenced by hardware to ensure device- specific power requirements are followed. Sequencing of specific voltages is required to ensure that devices using multiple voltages are not damaged or stressed.

Figure 8. Power Good Map

				Low Voltage
				Intel® Xeon™
				Processor
	VRM	VRM_PWRGOOD	H_PWRGD
	Controller		ICH3
			ICH3_PCIRST#	Low Voltage
				Intel® Xeon™
	Intelligent Platform			Processor
	Management
	Controller		E7501
	(IPMC)		MCH	ICH3_PCIRST#
				(global reset)
Power	PLD	ICH3_PWROK	82546
Goods			Dual
			GbEnet
				B0895-02

Technical Product Specification 61

Order #273817