8050D N/B Maintenance

The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment.

INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse

interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt controllers. Besides, the I/O APICSecretmanaging up to 14 i terrupts with both Serial and FSB interrupt delivery modes is supported.

The integrated power management module in orporates the ACPI 1.0b compliance functions, the APM 1.2

compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and

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power down events are also supported. 21 gener l purposed I/O pins are provided to give an easy to use logic for

specific application. In addition,MiTacthe INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel

Mobile processor.

 

A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM ICH4-M Hub terface together. Intel®’ I/O Hub architecture is developed

1.3.5 VGA Control

￿Introducing MOBILITY M10

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