Dedicated LVDS LCD Flat Panel Interface Signal Descriptions

8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(7)

Hub Interface Signals

Digital Video Output B (DVOB) Port Signal Descriptions

Signal Name

HL[10:0]

HLSTB

HLSTB#

Name

ICLKAP

ICLKAM

IYAP[3:0]

IYAM[3:0]

ICLKBP

ICLKBM

IYBP[3:0]

IYBM[3:0]

Type

 

 

Description

 

 

Name

Type

Description

 

I/O

Packet Data: Data signals used for HI read and write operations.

 

 

DVOBD[11:0]

O

DVOB Data: This data bus is used to drive 12-bit RGB data on each

 

Hub

 

 

 

 

 

 

DVO

edge of the differential clock signals, DVOBCLK and DVOBCLK#.

 

I/O

Packet Strobe: One of two differential strobe signals used to transmit

 

 

 

 

This provides 24-bits of data per clock period. In dual channel mode,

 

Hub

or receive packet data over HI.

 

 

 

 

this provides the lower 12-bits of pixel data.

 

I/O

Packet Strobe Complement: One of two differential strobe signals

 

 

 

 

DVOBD[11:0] should be left as left as NC (“Not Connected”) if not

 

Hub

used to transmit or receive packet data over HI.

 

 

 

 

used.

 

 

 

 

 

 

 

DVOBHSYNC

O

Horizontal Sync: HSYNC signal for the DVOB interface.

 

 

 

 

 

 

 

 

DVO

DVOBHSYNC should be left as left as NC (“Not Connected”) if not

 

 

 

 

 

 

 

 

 

used.

 

 

 

 

 

 

 

DVOBVSYNC

O

Vertical Sync: VSYNC signal for the DVOB interface.

 

 

 

 

 

 

 

 

DVO

DVOBVSYNC should be left as left as NC (“Not Connected”) if the

 

 

 

 

 

 

 

 

 

signal is NOT used when using internal graphics device.

 

 

 

 

 

 

 

DVOBBLANK#

O

Flicker Blank or Border Period Indication: DVOBBLANK# is a

Type

 

Voltage

 

Description

Secret

DVO

programmable output pin driven by the GMCH.

 

 

 

When programmed as a blank period indication, this pin indicates

O

1.25

V± 225 mV

Channel A differential clock pair output (true):

 

 

active pixels excluding the border. When programmed as a border

LVDS

 

 

245-800 MHz

 

 

period indication, this pin indicates active pixel including the border

O

1.25

V±225 mV

Channel A differential clock pair output

 

 

 

 

pixels.

LVDS

 

 

(compliment): 245-800 MHz.

 

 

 

 

DVOBBLANK# should be left as left as NC (“Not Connected”) if not

O

1.25

V±225 mV

Channel A differential data pair 3:0 output (true):

 

Documentused.

LVDS

 

 

245-800MHz.

 

 

 

DVOBFLDSTL

I

TV Field and Flat Panel Stall Signal. This input can be

O

1.25

V±225 mV

Channel A differential data pair 3:0 output

 

 

 

DVO

programmed to be either a TV Field input from the TV encoder or

LVDS

 

 

(compliment): 245-800 MHz.

 

 

 

 

Stall input from the flat panel.

O

1.25

V±225 mV

 

MiTac

 

 

 

DVOB TV Field Signal: When used as a Field input, it synchronizes

Channel B differential clock pair output (true):

 

 

 

 

LVDS

 

 

245-800 MHz.

 

 

 

 

 

the overlay field with the TV encoder field when the overlay is

O

1.25

V±225 mV

Channel B differential clock pa r output

 

 

 

 

displaying an interleaved source.

LVDS

 

 

(compliment): 245-800 MHz.

 

 

 

 

DVOB Flat Panel Stall Signal: When used as the Stall input, it

O

1.25

V±225 mV

Channel B differential data pair 3:0 output (true):

 

 

 

 

indicates that the pixel pipeline should stall one horizontal line. The

LVDS

 

 

245-800MHz.

 

 

 

 

 

signal changes during horizontal blanking. The panel fitting logic,

O

1.25

V± 225 mV

Channel B differential data pair 3:0 output

 

 

 

 

when expanding the image vertically, uses this.

LVDS

 

 

(compliment): 245-800 MHz.

 

 

 

 

DVOBFLDSTL needs to be pulled down if not used.

 

 

 

Confidential

 

 

 

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