Description
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the associated signals are inverted or not. DINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8.

8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(1)

Host Interface Signal Descriptions

Signal Name

Type

Description

ADS#

I/O

Address Strobe: The system bus owner asserts ADS# to indicate the

 

AGTL+

first of two cycles of a request phase. The GMCH can assert this

 

 

signal for snoop cycles and

 

 

interrupt messages.

Host Interface Signal Descriptions(Continued)

Signal Name

Type

DINV[3:0]#

I/O

 

AGTL+

BNR#I/O AGTL+

BPRI#O AGTL+

BREQ0#I/O AGTL+

CPURST# O AGTL+

DBSY#I/O AGTL+

DEFER#O AGTL+

Block Next Request: Used to block the current request bus owner

 

 

 

DINV# Data Bits

from issuing a new request. This signal is used to dynamically control

 

 

 

DINV[3]# HD[63:48]#

the CPU bus pipeline depth.

 

 

 

 

DINV[2]# HD[47:32]#

Bus Priority Request: The GMCH is the only Priority Agent on the

 

 

 

DINV[1]# HD[31:16]#

system bus. It asserts this signal to obtain the ownership of the

 

 

 

DINV[0]# HD[16:0]#

address bus. This signal has priority over symmetric bus requests and

 

DPSLP#

I

Deep Sleep #: This signal comes from the ICH4-M device, providing

will cause the current symmetric owner to

 

 

 

CMOS

an i dication of C3 and C4 state control to the CPU. Deassertion of

stop issuing new transactions unless the HLOCK# signal was

 

 

 

this signal is used as an early indication for C3 and C4 wake up (to

asserted.

 

 

 

 

active HPLL). Note that this is a low-voltage

Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal

 

 

 

CMOS buffer operating on the FSB VTT power plane.

low during CPURST#. The signal is sampled by the processor on the

 

DRDY#

I/O

Data Ready: Asserted for each cycle that data is transferred.

active-to-inactive transition of CPURST#. The minimum setup time

Secret

AGTL+

 

for this signal is 4 BCLKs. The minimum hold time is 2 clocks and

I/O

Host Address Bus: HA[31:3]# connects to the CPU address bus.

 

HA[31:3]#

the maximum hold time is 20 BCLKs. BREQ0# should be trist ted

 

 

 

AGTL+

During processor cycles the HA[31:3]# are inputs. The GMCH drives

after the hold time requirement has been satisfied.

 

 

 

 

 

HA[31:3]# during snoop cycles on behalf of Hub interface.

During regular operation, the GMCH will use BREQ0# as an early

 

Document

indication for FSB Address and Ctl input buffer and sense amp

 

 

 

HA[31:3]# are transferred at 2x rate. Note that the

 

 

 

address is inverted on the CPU bus.

activation.

 

 

 

 

 

 

HADSTB[1:0]#

I/O

Host Address Strobe: HA[31:3]# connects to the CPU address bus.

CPU Reset: The CPURST# pin is an output from the GMCH. The

 

 

 

AGTL+

During CPU cycles, the source synchronous strobes are used to

 

MiTac

 

GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M)

 

 

 

transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.

is asserted and for approximately 1 ms after RESET# is asserted.

 

 

 

 

 

 

Strobe Address Bits

The CPURST# allows the processor to begin execution in a known

 

 

 

 

 

 

HADSTB[0]# HA[16:3]#, HREQ[4:0]#

state.

 

 

 

 

 

 

 

 

HADSTB[1]# HA[31:17]#

Note that the ICH4-M must provide CPU strap set-up and hold-times

 

 

 

 

HD[63:0]#

I/O

Host Data: These signals are connected to the CPU data bus.

around CPURST#.

 

 

 

 

 

AGTL+

HD[63:0]# are transferred at 4x rate. Note that the data signals are

This requires strict synchronizati between GMCH, CPURST#

 

 

deassertion and ICH4-M driving the straps.

inverted on the CPU bus.

 

Data Bus Busy: Used by the data bus owner to hold the data bus for

 

transfers requiring more than one cycle.

 

Confidential

 

Defer: GMCH will generate a deferred response as defined by the

 

rules of the GMCH’s Dynamic Defer policy. The GMCH will also

 

use the DEFER# signal to indicate a CPU retry response.

 

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