MiTAC 8050D manual 85

EEPROM Interface Signals

LAN Connect Interface Signals

Description

Hub Interface Signals

Hub Interface Strobe/ Hub Interface Strobe Second: One of two differential strobe signals used to transmit and receive data through the hub interface.

Hub Interface 1.5 mode this signal is not differential and is the second of the two strobe signals.

8050D N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1)

Hub Interface Signals

Signal Name	Type
HI[11:0]	I/O
HI_STB/HI_STBS	I/O

Firmware Hub Interface Signals

Signal Name	Type	Description
FWH[3:0]/	I/O	Firmware Hub Signals. Muxed with LPC address signals.
LAD[3:0]	I/O	LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME#
FWH[4]/
LFRAME#		signal.

HI_STB#/I/O

HI_STBF

HICOMPI/O

HI_VSWING I

Signal Name	Type
LAN_CLK	I
LAN_RXD[2:0]	I
LAN_TXD[2:0]	O
LAN_RSTSYNC	O

Signal Name	Type
EE_SHCLK	O
EE_DIN	I
EE_DOUT	O
EE_CS	O

Hub Interface Strobe Complement / Hub Interface Strobe First:						PCI Interface Signals
One of two differential strobe signals used to transmit and receive						Signal Name	Type		Description
data through the hub interface.						AD[31:0]	I/O	PCI Address/Data: AD[31:0] is a multiplexed address and data
Hub Interface 1.5 mode this signal is not differential and is the first
								bus. During the first clock of a transaction, AD[31:0] contain a
of the two strobe signals.
								physical address (32 bits). During subsequent clocks, AD[31:0]
Hub Interface Compensation: Used for hub interface buffer
								contain data. The ICH4 drives all 0s on AD[31:0] during the address
compensation.
								phase of all PCI Special Cycles.
Hub Interface Voltage Swing: Analog input used to control the
						C/BE[3:0]#	I/O	Bus Command and Byte Enables: The command and byte enable
voltage swing and impedance strength of hub interface pins.				Secret				signals are multiplexed on the same PCI pins. During the address
								phase of a transaction, C/BE[3:0]# define the bus command. During
								the data phase, C/BE[3:0]# define the Byte Enables.
								C/BE[3:0]#	Command Type
	Description							0 0 0 0	Interrupt Acknowledge
					Document				Special Cycle
LAN I/F Clock: Driven by the LAN Connect component.								0 0 0 1
								0 0 1 0	I/O Read
Frequency range is 5 MHz to 50 MHz.
								0 0 1 1	I/O Write
Received Data: The LAN Connect component uses these sig als o
			MiTac					0 1 1 0	Memory Read
transfer data and control information to the integrat d LAN								0 1 1 1	Memory Write
Controller. These signals have integrated weak pull-up r sistors.
								1 0 1 0	Configuration Read
Transmit Data: The integrated LAN Controller uses these signals
								1 0 1 1	Configuration Write
to transfer data and control information to the LAN Connect
								1 1 0 0	Memory Read Multiple
component.
								1 1 1 0	Memory Read Line
LAN Reset/Sync: The LAN		ect component’s Reset and Sync
								1 1 1 1	Memory Write and Invalidate
signals are multiplexed onto this pin.
								All command encodings not shown are reserved. The ICH4 does not
	Confidential
								decode reserved values, and therefore will not respond if a PCI
						DEVSEL#	I/O	master generates a cycle using one of the reserved values.
	Description							Device Select: The ICH4 asserts DEVSEL# to claim a PCI
								transaction. As an output, the ICH4 asserts DEVSEL# when a PCI
EEPROM Shift Clock: Serial shift clock output to the EEPROM.								master peripheral attempts an access to an internal ICH4 address or
								an address destined for the hub interface (main memory or AGP).

EEPROM Data In: Transfers data from the EEPROM to the ICH3.	As an input, DEVSEL# indicates the response to an ICH4-initiated
This signal has an integrated pull-up resistor.
	transaction on the PCI bus. DEVSEL# is tri-stated from the leading
EEPROM Data Out: Transfers data from the ICH3 to the
	edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until
EEPROM.
	driven by a Target device.
EEPROM Chip Select: Chip select signal to the EEPROM.

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