8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(9)

GPIO Signal Descriptions

GPIO Signal Descriptions(Continued)

GPIO I/F Total

Type

RSTIN#

I

 

CMOS

PWROK

I

 

CMOS

AGPBUSY#

O

 

CMOS

EXTTS_0I CMOS

LCLKCTLA

O

 

CMOS

LCLKCTLB

O

 

CMOS

PANELVDDEN

O

 

CMOS

PANELBKLTE

O

N

CMOS

PANELBKLTC

O

TL

CMOS

DDCACLK

I/O

 

CMOS

DDCADATA

I/O

 

CMOS

DDCPCLK

I/O

 

CMOS

DDCPDATA

I/O

 

CMOS

CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and the GMCH.

 

Comments

 

 

GPIO I/F Total

Type

Comments

Reset: Primary Reset, Connected to PCIRST# of ICH4-M.

 

MI2CCLK

I/O

DVO I2C Clock: This signal is used as the I2C_CLK for a digital

 

 

 

 

 

DVO

display (i.e. TV-Out Encoder, TMDS transmitter). This signal is

Power OK: Indicates that power to GMCH is stable.

 

 

 

tri-stated during a hard reset.

 

 

 

 

MI2CDATA

I/O

DVO I2C Data: This signal is used as the I2C_DATA for a digital

AGPBUSY: Output of the GMCH IGD to the ICH4-M, which

 

 

DVO

display (i.e. TV-Out Encoder, TMDS transmitter). This signal is

indicates that certain graphics activity is taking place. It will indicate

 

 

 

tri-stated during a hard reset.

to the ACPI software not to enter the C3 state. It will

 

MDVICLK

I/O

DVI DDC Clock: This signal is used as the DDC clock for a digital

also cause a C3/C4 exit if C3/C4 was being entered, or was already

 

 

DVO

display connector (i.e. primary digital monitor). This signal is

entered when

 

 

 

 

 

tri-s a ed during a hard reset.

AGPBUSY# went active. Not active when the IGD is in any ACPI

 

MDVIDATA

I/O

DVI DDC Data: The signal is used as the DDC data for a digital

state other than D0.

 

 

 

 

DVO

display connector (i.e. primary digital monitor). This signal is

External Thermal Sensor Input: This signal is an active low input

 

 

 

tri-stated during a hard reset.

to the GMCH and is used to monitor the thermal condition around the

 

MDDCDATA

I/O

DVI DDC Clock: The signal is used as the DDC data for a digital

system memory and is used for triggering a read throttle. The GMCH

 

 

DVO

display connector (i.e. secondary digital monitor). This signal is

can be optionally programmed to send a SERR, SCI, or SMI message

 

 

 

tri-stated during a hard reset.

to the ICH4-M upon the triggering

 

 

MDDCCLK

I/O

DVI DDC Data: The signal is used as the DDC clock for a digital

of this signal.

 

 

Secret

DVO

display connector (i.e. secondary digital monitor). This signal is

SSC Chip Clock Control: Can be used to control an extern l clock

 

 

 

tri-stated during a hard reset.

chip with SSC control.

 

 

 

Document

SSC Chip Data Control: Can be used to control an external clock

 

chip for SSC control.

 

 

 

 

 

 

LVDS LCD Flat Panel Power Control: This signal is used enable

 

 

 

 

power to the panel interface.

MiTac

 

 

 

LVDS LCD Flat Panel Backlight Enable: This signal is used to

 

 

 

 

enable the backlight inverter (BLI)

 

 

 

 

 

LVDS LCD Flat Panel Backlight Brightness Control: This signal

 

 

 

 

is used as the Pulse

 

 

 

 

 

 

Width Modulated (PWM) control sig

to control the backlight

 

 

 

 

inverter.

Confidential

 

 

 

 

 

CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the GMCH.

Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the GMCH.

Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH.

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