8050D N/B Maintenance

5.Pin Descriptions of Major Components

5.1Intel Pentium M(Banias) Processor(1)

Signal Name

Type

A[31:3]#

I/O

A20M#I

ADS#I/O

ADSTB[1:0]# I/O

BCLK[1:0] I

BNR#I/O

BPM[2:0]# O

BPM[3]I/O

 

Description

 

Signal Name

Type

 

Description

 

A[31:3]# (Address) define a 2 32 -byte physical memory address space.

 

BPRI#

I

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the

In sub-phase 1 of the address phase, these pins transmit the address of a

 

 

 

processor system bus. It must connect the appropriate pins of both

transaction. In sub-phase 2, these pins transmit transaction type

 

 

 

processor system bus agents. Observing BPRI# active (as asserted by

information. These signals must connect the appropriate pins of both

 

 

 

the priority agent) causes the other agent to stop issuing new requests,

agents on the Intel Pentium M processor system bus. A[31:3]# are source

 

 

 

unless such requests are part of an ongoing locked operation. The

synchronous signals and are latched into the receiving buffers by

 

Document

 

 

Secret

 

priori y agent keeps BPRI# asserted until all of its requests are

boundary. Assertion of A20M# is only supported in real mode.

 

(1% tolerance) resistors. Refer to the platform design guides for more

ADSTB[1:0]#. Address signals are used as straps which are sampled

 

 

 

completed, then releases the bus by deasserting BPRI#.

before RESET# is deasserted.

 

BR0#

I/O

BR0# is used by the processor to request the bus. The arbitration is done

If A20M# (Address-20 Mask) is asserted, the processor masks physical

 

 

 

between the Intel Pentium M processor (Symmetric Agent) and the

address bit 20 (A20#) before looking up a line in any internal cache and

 

 

 

MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM

before driving a read/write transaction on the bus. Asserting A20M#

 

 

 

chipset.

 

 

emulates the 8086 processor's address wrap-around at the 1-Mbyte

 

COMPP3:0]

Analog

COMP[3:0] must be terminated on the system board using precision

 

MiTac

 

 

implementation details.

 

A20M# is an asynchronous signal. However, to ensure recognition of

 

 

 

 

this signal following an Input/Output write instruction, it must be v lid

 

[63:0]#

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data

along with the TRDY# assertion of the corresponding Input/Output

 

 

 

path between the processor system bus agents, and must connect the

Write bus transaction.

Confidential

 

appropriate pins on both agents. The data driver asserts DRDY# to

ADS# (Address Strobe) is asserted to indicate the validity of the

 

 

 

indicate a valid data transfer.

 

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agen s

 

 

 

D[63:0]# are quad-pumped signals and will thus be driven four times in

observe the ADS# activation to begin parity checking, protocol

 

 

 

a common clock period. D[63:0]# are latched off the falling edge of

checking, address decode, internal snoop, or deferred r ply ID match

 

 

 

both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals

operations associated with the new transaction.

 

 

 

correspond to a pair of one DSTBP# and one DSTBN#. The following

Address strobes are used to latch A[31:3]# and REQ[4:0]# their rising

 

 

 

table shows the grouping of data signals to data strobes and DINV#.

and falling edges. Strobes are associated with s gnals as shown below.

 

 

 

Quad-Pumped Signal Groups

 

Signals

Associated Strobe

 

 

 

Data Group

DSTBN#/DSTBP#

DINV#

REQ[4:0]#, A[16:3]#

ADSTB[0]#

 

 

 

D[15:0]#

0

0

A[31:17]#

ADSTB[1]#

 

 

 

D[31:16]#

1

1

The differential pair BCLK (Bus lock) determines the system bus

 

 

 

D[47:32]#

2

2

frequency. All processor system bus agents must receive these signals to

 

 

 

D[63:48]#

3

3

drive their outputs and latch their inputs.

 

 

 

Furthermore, the DINV# pins determine the polarity of the data signals.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent

 

 

 

Each group of 16 data signals corresponds to one DINV# signal. When

that is unable to accept new bus transactions. During a bus stall, the

 

 

 

the DINV# signal is active, the corresponding data group is inverted and

current bus owner cannot issue any new transactions.

 

 

 

therefore sampled active high.

 

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

 

DBR#

O

DBR# (Data Bus Reset) is used only in processor systems where no

monitor signals. They are outputs from the processor that indicate the

 

 

 

debug port is implemented on the system board. DBR# is used by a

status of breakpoints and programmable counters used for monitoring

 

 

 

debug port interposer so that an in-target probe can drive system reset. If

processor performance. BPM[3:0]# should connect the appropriate pins

 

 

 

a debug port is implemented in the system, DBR# is a no connect.

of all Intel Pentium M processor system bus agents. This includes debug

 

 

 

DBR# is not a processor signal.

 

or performance monitoring tools.

 

 

 

 

 

 

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