8050D N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(8)

AC’97 Link Signals

 

 

 

 

 

Power and Ground Signals

Signal Name

Type

 

Description

 

 

 

Signal Name

Description

AC_RST#

O

AC ’97 Reset: This signal is a master hardware reset to external

 

 

VCC3_3

3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5

 

 

Codec(s).

 

 

 

 

 

or G3 states.

AC_SYNC

O

AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the

 

 

VCC1_5

1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3

 

 

Codec(s).

 

 

 

 

 

states.

AC_BIT_CLK

I

AC97 Bit Clock: This signal is a 12.288 MHz serial data clock

 

 

VCCHI

1.5 V supply for Hub Interface 1.5 logic.

 

 

generated by the external Codec(s). This signal has an integrated

 

 

 

1.8 V supply for Hub Interface 1.0 logic.

 

 

pull-down resistor.

 

 

 

 

 

This power may be shut off in S3, S4, S5 or G3 states.

AC_SDOUT

O

AC97 Serial Data Out: Serial TDM data output to the Codec(s).

 

 

V5REF

Reference for 5 V olerance on core well inputs. This power may be shut off in

 

 

NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a

 

 

 

S3, S4, S5 or G3 s a es.

 

 

functional strap.

 

 

 

 

HIREF

Analog I put. Expected voltages are:

AC_SDIN[1:0]

I

AC97 Serial Data In 2:0: These signals are Serial TDM data inputs

 

 

 

• 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination

 

 

from the three Codecs.

 

 

 

 

 

• 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination

NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK

 

 

 

This power is shut off in S3, S4, S5, and G3 states.

Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of

 

 

VCCSUS3 3

3.3 V supply for resume well I/O buffers. This power is not expected to be shut

Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled.

Secret

off unless the main battery is removed or completely drained and AC power is

 

 

 

 

 

not available.

 

 

 

 

 

1.5 V supply for resume well logic. This power is not expected to be shut off

General Purpose I/O Signals

 

 

 

 

VCCSUS1 5

 

 

 

 

 

unless the main battery is removed or completely drained and AC power is not

Signal Name

Type

 

Description

 

 

Documentavailable.

GPIO[43:32]

I/O

Can be input or output. Main power well.

 

 

V5REF_SUS

Reference for 5 V tolerance on resume well inputs. This power is not expected

 

 

 

to be shut off unless the main battery is removed or completely drained and AC

GPIO[31:29]

O

Not implemented.

 

 

 

 

 

 

 

 

 

 

power is not available.

GPIO[28:27]

I/O

Can be input or output. Resume power well. Unmuxed.

 

 

 

 

 

VCCLAN3_3

3.3 V supply for LAN Connect interface buffers. This is a separate power plane

GPIO[26]

I/O

Not implemented.

 

MiTac

 

 

 

 

 

 

that may or may not be powered in S3–S5 states depending upon the presence or

GPIO[25]

I/O

Can be input or output. Resume power well. Unmux .

 

 

 

 

 

 

absence of AC power and network connectivity. This plane must be on in S0 and

GPIO[24:18]

I/O

Not Implemented in Mobile (Assign to nat ve Functionality).

 

 

 

S1-M.

GPIO[17:16]

O

Fixed as Output only. Main power well. Can be used instead as

 

 

VCCLAN1_5

1.5 V supply for LAN Controller logic. This is a separate power plane that may

 

 

PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for

 

 

 

or may not be powered in S3–S5 states depending upon the presence or absence

 

 

PCI GNT[5]#. Integrated pull-up resistor.

 

 

 

of AC power and network connectivity. This plane must be on in S0 and S1-M.

GPIO[15:14]

I

Not implemented.

 

 

 

 

VCCRTC

3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power

GPIO[13:12]

I

Fixed as Input only. Resume power well. Unmuxed.

 

 

 

is not expected to be shut off unless the RTC battery is removed or completely

GPIO[11]

I

Fixed as Input only. Resume power well. Can be used instead as

 

 

 

drained.

 

 

SMBALERT#.

Confidential

 

NOTE: Implementations should not attempt to clear CMOS by using a jumper

GPIO[10:9]

I

Not implemented.

 

 

 

 

 

to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done

GPIO[8]

I

Fixed as Input only. Resume power well. Unmuxed.

 

 

 

by using a jumper on RTCRST# or GPI, or using SAFEMODE strap.

GPIO[7]

I

Fixed as Input only. Main power well. Unmuxed.

 

 

VCCPLL

1.5 V supply for core well logic. This signal is used for the USB PLL. This

GPIO[6]

I

Not Implemented in Mobile (Assign to Native Functionality)

 

 

 

power may be shut off in S3, S4, S5 or G3 states.

 

 

VBIAS

RTC well bias voltage. The DC reference voltage applied to this pin sets a

GPIO[5:2]

I

Fixed as Input only. Main power well. Can be used instead as

 

 

 

 

 

current that is mirrored throughout the oscillator and buffer circuitry.

 

 

PIRQ[E:H]#.

 

 

 

 

 

 

 

 

 

 

 

V_CPU_IO

Powered by the same supply as the processor I/O voltage. This supply is used to

GPIO[1:0]

I

Fixed as Input only. Main power well. Can be used instead as

 

 

 

 

 

drive the processor interface outputs.

 

 

PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI

 

 

 

 

 

 

 

VSS

Grounds.

 

 

REQ[5]#.

 

 

 

 

NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO

 

 

 

91

are not 5V tolerant.