8050D N/B Maintenance
DQS
Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/received with
Four internal device banks for concurrent operation
Selectable burst lengths: 2, 4, or 8 |
| Document |
Auto precharge option | Secret | |
Auto Refresh and Self Refresh Modes |
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MiTac |
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15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD, | ||
Confidential |
MT8VDDT6464HD) maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM Fast data transfer rates PC2100 or PC1600
Selectable READ CAS latency for maximum compatibility
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