
8050D N/B Maintenance
5.2 Intel 855GM/GME North Bridge(5)
AGP/PCI | AGP Strobe Descriptions | ||||
Signal Name | Type | Description | Signal Name | Type | Description |
GFRAME# | I/O | G_FRAME: Frame. | GADSTB[0] | I/O | Address/Data Bus |
| AGP | During PIPE# and SBA Operation: Not used by AGP SBA and |
| AGP | AD[15:0] and C/BE[1:0]# signals. The agent that is providing the |
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| PIPE# operations. |
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| data will drive this signal. |
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| During Fast Write Operation: Used to frame transactions as an | GADSTB#[0] | I/O | Address/Data Bus |
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| output during Fast Writes. |
| AGP | differential strobe pair that provides timing information for the |
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| AD[15:0] and C/BE[1:0]# signals. The agent that is providing the |
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| data will drive this signal. |
GIRDY# | I/O |
| AGP |
acts as a |
| GADSTB[1] | I/O | Address/Data Bus | |||
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| Secret | AGP | AD[31:16] and C/BE[3:2]# signals. The agent that is providing the | ||
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| data will drive this signal. | |
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| GADSTB#[1] | I/O | Address/Data Bus | |
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| AGP | differential strobe pair that provides timing information for the | |
G_IRDY#: Initiator Ready. |
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| AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is | |
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| providing the data will drive this signal. | ||
During PIPE# and SBA Operation: Not used while enqueueing |
| GSBSTB | I | Sideband Strobe: Provides timing for 2x and 4x data on the | |||
requests via AGP SBA and PIPE#, but used during the data phase of |
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| AGP | SBA[7:0] bus. It is driven by the AGP master after the system has | |||
PIPE# and SBA transactions. | MiTac |
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| been configured for 2x or 4x sideband address mode. | |||
During FRAME# Operation: G_IRDY# is an output when GMCH |
| GSBSTB# | I | Sideband Strobe Complement: The differential complement to the | |||
acts as a |
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| AGP | SB STB signal. It is used to provide timing 4x mode. | |||
Confidential | |||||||
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indicates the current |
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complete the current data phase of the transaction. |
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During Fast Write Operation: In Fast Write mode, G IRDY# |
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indicates that the |
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data for the current transaction. Once G IRDY# is ass rt for write |
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operation, the master is not allowed to insert wait stat s. The master is |
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never allowed to insert a wait state during the | n t al ata transfer (32 |
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bytes) of a write transaction. However, it may | nsert wait states after |
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each |
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