8050D N/B Maintenance
5.1 Intel Pentium M(Banias) Processor(2)
Signal Name | Type |
DBSY# | I/O |
DEFER# | I |
DINV[3:0]# | I/O |
DPSLP#I
DRDY#I/O
DSTBN[3:0]# I/O
DSTBP[3:0]# I/O
| Description |
| Signal Name | Type | Description | ||
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving |
| DPWR# | I | DPWR# is a control signal from the Intel 855PM and Intel 855GM | |||
data on the processor system bus to indicate that the data bus is in use. |
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| chipsets used to reduce power on the Intel Pentium M data bus input | |||
The data bus is released after DBSY# is deasserted. This signal must |
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| buffers. | |||
connect the appropriate pins on both processor system bus agents. |
| FERR#/PBE# | O | FERR# | |||
DEFER# is asserted by an agent to indicate that a transaction cannot be |
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| multiplexed signal and its meaning is qualified by STPCLK#. When | |||
guaranteed |
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| STPCLK# is not asserted, FERR#/PBE# indicates a floating point when | |||
responsibility of the addressed memory or Input/Output agent. This |
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| the processor detects an unmasked | |||
signal must connect the appropriate pins of both processor system bus |
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| similar he ERROR# signal on the Intel 80387 coprocessor, and is | |||
agents. |
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| included for compatibility with systems using |
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate |
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| floati | |||
the polarity of the D[63:0]# signals. The DINV[3:0]# signals are |
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| of FERR#/PBE# indicates that the processor has a pending break event | |||
activated when the data on the data bus is inverted. The bus agent will |
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| waiting for service. The assertion of FERR#/PBE# indicates that the | |||
invert the data bus signals if more than half the bits, within the covered |
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| processor should be returned to the Normal state. When FERR#/PBE# is | |||
group, would change level in the next cycle. |
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| asserted, indicating a break event, it will remain asserted until | |||
DINV[3:0]# Assignment To Data Bus |
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| STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active | |||
Bus Signal | Data Bus Signals |
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| will also cause an FERR# break event. | ||
| GTLREF | I | GTLREF determines the signal reference level for AGTL+ input pins. | ||||
DINV[3]# | D[63:48]# |
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DINV[2]# | D[47:32]# |
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| GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ |
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| receivers to determine if a signal is a logical 0 or logical 1. | ||
DINV[1]# | D[31:16]# |
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| Confidential | HIT# | I/O | exception on a noncontrol | |||
DINV[0]# | D[15:0]# |
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| HITM# | I/O | operation results. Either system bus agent may assert both HIT# and |
DPSLP# when asserted on the platform causes the processor to |
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| HITM# together to indicate that it requires a snoop stall, which can be | |||
transition from the Sleep state to the Deep Sleep state. In order to re urn |
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| continued by reasserting HIT# and HITM# together. | |||
to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the |
| IERR# | O | IERR# (Internal Error) is asserted by a processor as the result of an | |||
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| internal error. Assertion of IERR# is usually accompanied by a | ||||
Intel 855PM or Intel 855GM chipset. |
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| SHUTDOWN transaction on the processor system bus. This transaction | |||
DRDY# (Data Ready) is asserted by the data dr ver on each data |
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| may optionally be converted to an external error signal (e.g., NMI) by | |||
transfer, indicating valid data | the data bus. In a |
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| system core logic. The processor will keep IERR# asserted until the | ||||
data transfer, DRDY# may be deasserted to i sert idle clocks. This |
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| assertion of RESET#, BINIT#, or INIT#. | ||||
signal must connect the appropriate pi s of both processor system bus |
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| IGNNE# | I | IGNNE# (Ignore Numeric Error) is asserted to force the processor to | ||||
agents. |
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| ignore a numeric error and continue to execute noncontrol | |
Data strobe used to latch in D[63:0]#. |
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| instructions. If IGNNE# is deasserted, the processor generates an | ||||
Signals |
| Associated Strobe |
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D[15:0]#, DINV[0]# | DSTBN[0]# |
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D[31:16]#, DINV[1]# | DSTBN[1]# |
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| the NE bit in control register 0 (CR0) is set. | ||
D[47:32]#, DINV[2]# | DSTBN[2]# |
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| IGNNE# is an asynchronous signal. However, to ensure recognition of | ||
D[63:48]#, DINV[3]# | DSTBN[3]# |
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| this signal following an Input/Output write instruction, it must be valid | ||
Data strobe used to latch in D[63:0]#. |
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| along with the TRDY# assertion of the corresponding Input/Output | |||
Signals |
| Associated Strobe |
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| Write bus transaction. | |
D[15:0]#, DINV[0]# | DSTBP[0]# |
| REQ[4:0]# | I/O | REQ[4:0]# (Request Command) must connect the appropriate pins of | ||
D[31:16]#, DINV[1]# | DSTBP[1]# |
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| both processor system bus agents. They are asserted by the current bus | ||
D[47:32]#, DINV[2]# | DSTBP[2]# |
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| owner to define the currently active transaction type. These signals are | ||
D[63:48]#, DINV[3]# | DSTBP[3]# |
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| source synchronous to ADSTB[0]#. | ||
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