8050D N/B Maintenance

5.1 Intel Pentium M(Banias) Processor(2)

Signal Name

Type

DBSY#

I/O

DEFER#

I

DINV[3:0]#

I/O

DPSLP#I

DRDY#I/O

DSTBN[3:0]# I/O

DSTBP[3:0]# I/O

 

Description

 

Signal Name

Type

Description

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving

 

DPWR#

I

DPWR# is a control signal from the Intel 855PM and Intel 855GM

data on the processor system bus to indicate that the data bus is in use.

 

 

 

chipsets used to reduce power on the Intel Pentium M data bus input

The data bus is released after DBSY# is deasserted. This signal must

 

 

 

buffers.

connect the appropriate pins on both processor system bus agents.

 

FERR#/PBE#

O

FERR# (Floating-point Error)/PBE#(Pending Break Event) is a

DEFER# is asserted by an agent to indicate that a transaction cannot be

 

 

 

multiplexed signal and its meaning is qualified by STPCLK#. When

guaranteed in-order completion. Assertion of DEFER# is normally the

 

 

 

STPCLK# is not asserted, FERR#/PBE# indicates a floating point when

responsibility of the addressed memory or Input/Output agent. This

 

 

 

the processor detects an unmasked floating-point error. FERR# is

signal must connect the appropriate pins of both processor system bus

 

 

 

similar he ERROR# signal on the Intel 80387 coprocessor, and is

agents.

 

 

 

 

 

 

included for compatibility with systems using MS-DOS* type

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate

 

 

 

floati g-point error reporting. When STPCLK# is asserted, an assertion

the polarity of the D[63:0]# signals. The DINV[3:0]# signals are

 

 

 

of FERR#/PBE# indicates that the processor has a pending break event

activated when the data on the data bus is inverted. The bus agent will

 

 

 

waiting for service. The assertion of FERR#/PBE# indicates that the

invert the data bus signals if more than half the bits, within the covered

 

 

 

processor should be returned to the Normal state. When FERR#/PBE# is

group, would change level in the next cycle.

 

 

 

asserted, indicating a break event, it will remain asserted until

DINV[3:0]# Assignment To Data Bus

 

 

 

STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active

Bus Signal

Data Bus Signals

 

 

 

will also cause an FERR# break event.

 

GTLREF

I

GTLREF determines the signal reference level for AGTL+ input pins.

DINV[3]#

D[63:48]#

 

 

 

DINV[2]#

D[47:32]#

 

 

 

 

 

GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+

 

 

 

 

 

receivers to determine if a signal is a logical 0 or logical 1.

DINV[1]#

D[31:16]#

 

 

 

 

 

 

 

Document

 

Confidential

HIT#

I/O

exception on a noncontrol floating-point instruction if a previous

DINV[0]#

D[15:0]#

 

 

 

HITM#

I/O

operation results. Either system bus agent may assert both HIT# and

DPSLP# when asserted on the platform causes the processor to

 

 

 

HITM# together to indicate that it requires a snoop stall, which can be

transition from the Sleep state to the Deep Sleep state. In order to re urn

 

 

 

continued by reasserting HIT# and HITM# together.

to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the

 

IERR#

O

IERR# (Internal Error) is asserted by a processor as the result of an

ICH4-M component and also connects to the MCH-M compo e t of the

 

 

 

internal error. Assertion of IERR# is usually accompanied by a

Intel 855PM or Intel 855GM chipset.

 

 

 

SHUTDOWN transaction on the processor system bus. This transaction

DRDY# (Data Ready) is asserted by the data dr ver on each data

 

 

 

may optionally be converted to an external error signal (e.g., NMI) by

transfer, indicating valid data

the data bus. In a multi-common clock

 

 

 

 

 

 

system core logic. The processor will keep IERR# asserted until the

data transfer, DRDY# may be deasserted to i sert idle clocks. This

 

 

 

 

 

 

assertion of RESET#, BINIT#, or INIT#.

signal must connect the appropriate pi s of both processor system bus

 

 

 

 

IGNNE#

I

IGNNE# (Ignore Numeric Error) is asserted to force the processor to

agents.

 

 

 

 

 

 

 

 

 

 

ignore a numeric error and continue to execute noncontrol floating-point

Data strobe used to latch in D[63:0]#.

 

 

 

 

 

 

instructions. If IGNNE# is deasserted, the processor generates an

Signals

 

Associated Strobe

 

 

 

 

 

 

 

 

D[15:0]#, DINV[0]#

DSTBN[0]#

 

 

 

floating-point instruction caused an error. IGNNE# has no effect when

D[31:16]#, DINV[1]#

DSTBN[1]#

 

 

 

the NE bit in control register 0 (CR0) is set.

D[47:32]#, DINV[2]#

DSTBN[2]#

 

 

 

IGNNE# is an asynchronous signal. However, to ensure recognition of

D[63:48]#, DINV[3]#

DSTBN[3]#

 

 

 

this signal following an Input/Output write instruction, it must be valid

Data strobe used to latch in D[63:0]#.

 

 

 

along with the TRDY# assertion of the corresponding Input/Output

Signals

 

Associated Strobe

 

 

 

Write bus transaction.

D[15:0]#, DINV[0]#

DSTBP[0]#

 

REQ[4:0]#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of

D[31:16]#, DINV[1]#

DSTBP[1]#

 

 

 

both processor system bus agents. They are asserted by the current bus

D[47:32]#, DINV[2]#

DSTBP[2]#

 

 

 

owner to define the currently active transaction type. These signals are

D[63:48]#, DINV[3]#

DSTBP[3]#

 

 

 

source synchronous to ADSTB[0]#.

 

 

 

 

 

 

 

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