8050D N/B Maintenance

5.1 Intel Pentium M(Banias) Processor(4)

Signal Name

Type

SMI#

I

STPCLK# I

TCKI

TDII

TDOO

TEST1,I

TEST2,

TEST3

THERMDA Other

THERMDC Other

THERMTRIP# O

TMSI

TRDY#I

TRST#I

Description

Signal Name

Type

Description

SMI# (System Management Interrupt) is asserted asynchronously by

VCC

I

Processor core power supply.

system logic. On accepting a System Management Interrupt, the

VCCA[3:0]

I

VCCA provides isolated power for the internal processor core PLL’s.

processor saves the current state and enter System Management Mode

VCCP

I

Processor I/O Power Supply.

(SMM). An SMI Acknowledge transaction is issued, and the processor

VCCQ[1:0]

I

Quiet power supply for on die COMP circuitry. These pins should be

begins program execution from the SMM handler.

 

 

connected to VCCP on the motherboard. However, these connections

If SMI# is asserted during the deassertion of RESET# the processor will

VCCSENSE

O

should enable addition of decoupling on the VCCQ lines if necessary.

tristate its outputs.

VCCSENSE is an isolated low impedance connection to processor core

 

 

power (VCC ). It can be used to sense or measure power near the silicon

STPCLK# (Stop Clock), when asserted, causes the processor to enter a

 

 

 

 

with li le noise.

low power Stop-Grant state. The processor issues a Stop-Grant

 

 

VID[5:0]

O

VID[5:0] (Vol age ID) pins are used to support automatic selection of

Acknowledge transaction, and stops providing internal clock signals to

Secret

 

pow r supply voltages (Vcc). Unlike some previous generations of

all processor core units except the system bus and APIC units. The

 

 

proc ssors, these are CMOS signals that are driven by the Intel Pentium

processor continues to snoop bus transactions and service interrupts

 

 

M processor. The voltage supply for these pins must be valid before the

while in Stop-Grant state. When STPCLK# is deasserted, the processor

 

VR can supply Vcc to the processor. Conversely, the VR output must be

restarts its internal clock to all units and resumes execution. The

 

disabled until the voltage supply for the VID pins becomes valid. The

assertion of STPCLK# has no effect on the bus clock; STPCLK# is an

 

VID pins are needed to support the processor voltage specification

asynchronous input.

 

variations.

TCK (Test Clock) provides the clock input for the processor Test Bus

O

VSSSENSE is an isolated low impedance connection to processor core

VSSSENSE

(also known as the Test Access Port).

 

 

VSS. It can be used to sense or measure ground near the silicon with

TDI (Test Data In) transfers serial test data into the processor. DI

 

 

little noise.

provides the serial input needed for JTAG specificat support.

Document

 

 

 

TEST1, TEST2, and TEST3 must be left unconnected but should have stuffing option connection to V SS separately using 1-k, pull-down resisitors.

MiTac TDO (Test Data Out) transfersConfidentialserial test data out of the processor. TDO provides the serial output needed for JTAG specification support.

Thermal Diode Anode.

Thermal Diode Cathode.

The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sens r is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.

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