8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(3)

DDR SDRAM Interface Descriptions (Continued)

AGP Addressing Signal Descriptions

Signal Name

Type

SDQS[8:0]

I/O

 

SSTL_2

SCKE[3:0] O SSTL_2

SMAB[5,4,2,1] O SSTL_2

SDM[8:0] O SSTL_2

RCVENOUT# O SSTL_2

RCVENIN# O SSTL_2

 

Description

 

 

Signal Name

Type

Description

Data Strobes: Data strobes are used for capturing data. During

 

 

GPIPE#

I

Pipelined Read: This signal is asserted by the AGP master to

writes, SDQS is centered on data. During reads, SDQS is edge

 

 

 

AGP

indicate a full width address is to be enqueued on by the target using

aligned with data. The following list matches the data strobe with the

 

 

 

 

the AD bus. One address is placed

data bytes.

 

 

 

 

 

in the AGP request queue on each rising clock edge while PIPE# is

There is an associated data strobe (DQS) for each data signal (DQ)

 

 

 

 

asserted. When PIPE# is deasserted no new requests are queued

and check bit

 

 

 

 

 

across the AD bus.

(CB) group.

 

 

 

 

 

During SBA Operation: This signal is not used if SBA (Side Band

SDQS[7] -> SDQ[63:56]

 

 

 

 

 

Addressing) is selected.

DDR SDRAM rows. There is one

 

DocumentDuring FRAME# Operation: These signals are not used during

SDQS[6] -> SDQ[55:48]

 

Secret

 

During FRAME# Operation: This signal is not used during AGP

Clock Enable: These pins are used to signal self-refresh or power

 

AD bus simultaneously.

SDQS[5] -> SDQ[47:40]

 

 

 

 

 

FRAME# operation.

SDQS[4] -> SDQ[39:32]

 

 

 

 

 

PIPE# is a sustained tri-state signal from masters (graphics

SDQS[3] -> SDQ[31:24]

 

 

 

 

 

controller), and is an input to the GMCH.

SDQS[2] -> SDQ[23:16]

 

 

 

GSBA[7:0]

I

Side-band Address: These signals are used by the AGP master

SDQS[1] -> SDQ[15:8]

 

 

 

 

AGP

(graphics controller) to pass address and command to the GMCH. The

SDQS[0] -> SDQ[7:0]

 

 

 

 

 

SBA bus and AD bus operate independently. That is, transactions can

NOTE: ECC error detection is supported by the SDQS[8] signal.

 

 

 

 

proceed on the SBA bus and the

down command to the DDR SDRAM array when entering system

 

 

 

 

During PIPE# Operation: These signals are not used during PIPE#

suspend. SCKE is also used to dynamically power down in ctive

 

 

 

 

operation.

 

Confidential

 

 

 

SCKE per DDR SDRAM row. These signals can be toggled on every

 

 

 

 

AGP FRAME# operation.

rising SCK edge.

 

 

 

 

 

NOTE: When sideband addressing is disabled, these signals are

Memory Address Copies: These signals areMiTacidentical to

 

 

 

isolated (no external/internal pull-ups are required).

SMA[5,4,2,1] and are used to reduce loading for selective

 

 

5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use

CPC(clock-per-command). These copies are not inv rt .

 

 

one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is

Data Mask: When activated during writes, the corr sponding data

 

 

used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example,

groups in the DDR SDRAM are masked. There s one SDM for every

 

 

during configuration time, if the master indicates that it can use either mechanism, the configuration

eight data lines. SDM can be sampled on both edges of the data

 

 

software will indicate which mechanism the master will use. Once this choice has been made, the

strobes.

 

 

 

master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use

NOTE: ECC error detection is supp rted by the SDM[8] signal.

 

 

the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when

Clock Output: Reserved, NC.

 

 

the device is first being configured after reset

Clock Input: Reserved, NC.

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