MiTAC 8050D manual 91

System Management Interface Signals

CPU Power Good: This signal should be connected to the processor’s PWRGOOD input. To allow for Intel ® SpeedStep™ technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH4’s PWROK and VGATE / VRMPWRGD signals.

Deeper Sleep: This signal is asserted by the ICH4 to the processor. When the signal is low, the processor enters the Deeper Sleep state by gating off the processor Core clock inside the processor. When the signal is high (default), the processor is not in the Deeper Sleep state. This signal behaves identically to the STP_CPU# signal, but at the processor voltage level.

8050D N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(7)

Processor Interface Signals (Continued)			Real Time Clock Interface Signals
Signal Name	Type	Description	Signal Name	Type	Description
CPUPWRGD	OD		RTCX1	Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal.
			RTCX2	Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal.

Other Clock Signals

DPSLP#O

SMBus Interface Signals

Signal Name	Type
SMBDATA	I/OD
SMBCLK	I/OD
SMBALERT#/	I
GPIO[11]

Signal Name	Type
INTRUDER#	I

SMLINK[1:0] I/OD

Signal Name TypeDescription

			Document
			CLK14	I	Oscilla or Clock: Used for 8254 timers. It runs at 14.31818 MHz.
		Secret			This clock is permitted to stop during S1-M (or lower) states.
			CLK48	I	48 MHz Clock: This clock is used to run the USB controller. It runs
					at 48 MHz. This clock is permitted to stop during S1-M (or lower)
					states.
			CLK66	I	66 MHz Clock: This is used to run the hub interface. It runs at 66
	MiTac				MHz. This clock is permitted to stop during S1-M (or lower) states.
Description			Miscellaneous Signals
			Signal Name	Type		Description
SMBus Data: External pull-up is required.
					Implementations should not attempt to clear CMOS by using a
System Management Link:ConfidentialSMBus link to optional external				O
SMBus Clock: External pull-up is required.			SPKR		Speaker: The SPKR signal is the output of counter 2 and is
					internally “ANDed” with Port 61h bit 1 to provide Speaker Data
SMBus Alert: This signal is used to wake the system or genera e					Enable. This signal drives an external speaker driver device, which
SMI#. If not used for SMBALERT#, it can be used as		GPI.			in turn drives the system speaker. Upon PCIRST#, its output state is
					0.
					NOTE: SPKR is sampled at the rising edge of PWROK as a
					functional strap.
			RTCRST#	I	RTC Reset: When asserted, this signal resets register bits in the
Description					RTC well and sets the RTC_PWR_STS bit (bit 2 in
					GEN_PMCON3 register).
Intruder Detect: Can be set to disable system if box detected open.
					NOTES:
This signal’s status is readable, so it can be used like		GPI if the			1. Clearing CMOS in an ICH4-based platform can be done by using
Intruder Detection is not needed.					a jumper on RTCRST# or GPI, or using SAFEMODE strap.
system management ASIC or LAN controller. External pull-ups are					jumper to pull VccRTC low.
required.					2. Unless entering the XOR Chain Test Mode, the RTCRST# input
Note that SMLINK[0] corresponds to an SMBus Clock signal, and					must always be high when all other RTC power planes are on.
SMLINK[1] corresponds to an SMBus Data signal.

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