MiTAC 8050D manual 77

8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(2)

Host Interface Signal Descriptions (Continued) DDR SDRAM Interface Descriptions

Signal Name	Type
HDSTBP[3:0]#	I/O
HDSTBN[3:0]#	AGTL+

HIT#	I/O
	AGTL+
HITM#	I/O
	AGTL+
HLOCK#	I/O
	AGTL+
HREQ[4:0]#	I/O
	AGTL+

HTRDY#O AGTL+

RS[2:0]#O AGTL+

Description				Signal Name	Type	Description
Differential Host Data Strobes: The differential source synchronous				SCS[3:0]#	O	Chip Select: These pins select the particular DDR SDRAM
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x					SSTL_2 components during the active state.
transfer rate.						NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM
Strobe Data Bits						device row.
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#						These signals can be toggled on every rising System Memory Clock
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]#						edge (SCMDCLK).
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]#				SMA[12:0]	O	Multiplexed Memory Address: These signals are used to provide
HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]#					SSTL 2	the mul iplexed row and column address to the DDR SDRAM.
Hit: Indicates that a caching agent holds an unmodified version of the				SBA[1:0]	O	Bank Select (Memory Bank Address): These signals define which
requested line. Also, driven in conjunction with HITM# by the target					SSTL 2	ba ks are selected within each DDR SDRAM row. The SMA and
to extend the snoop window.						SBA signals combine to address every possible location within a
Hit Modified: Indicates that a caching agent holds a modified version						DDR SDRAM device.
of the requested line and that this agent assumes responsibility for				SRAS#	O	DDR Row Address Strobe: SRAS# may be heavily loaded and
providing the line.			Secret		SSTL 2	requires tw0 DDR SDRAM clock cycles for setup time to the DDR
Also, driven in conjunction with HIT# to extend the snoop window.						SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define
Host Lock: All CPU bus cycles sampled with the assertion of						the system memory commands.
HLOCK# and ADS#, until the negation of HLOCK# must be atomi ,					O	DDR Column Address Strobe: SCAS# may be heavily loaded and
				SCAS#
i.e. no Hub interface snoopable access to system memory is		llowed			SSTL 2	requires two clock cycles for setup time to the DDR SDRAMs. Used
when HLOCK# is asserted by the CPU.				Documentwith SRAS# and SWE# (along with SCS#) to define the system
Host Request Command: Defines the attributes of the request.						memory commands.
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting				SWE#	O	Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
agent during both halves of the Request Phase. In the first half he					SSTL_2 define the DDR SDRAM commands. SWE# is asserted during writes
signals define the transaction type to a level of						to DDR SDRAM.
	MiTac
detail that is sufficient to begin a snoop request. In the s co		d half the				SWE# may be heavily loaded and requires two clock cycles for setup
signals carry additional information to define the compl te transaction						time to the DDR SDRAMs.
type.				SDQ[71:0]	I/O	Data Lines: These signals are used to interface to the DDR SDRAM
The transactions supported by the GMCH Host Bri ge are defined in					SSTL_2	data bus.
the Host Interface section of this document.						NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
Host Target Ready: Indicates that the target of the processor
transaction is able to enter the data tra	sfer phase.
Response Status: Indicates the type	response according to the

following the table: Confidential

RS[2:0]# Response type 000 Idle state

001 Retry response

010 Deferred response

011 Reserved (not driven by GMCH)

100 Hard Failure (not driven by GMCH)

101 No data response

110 Implicit Write back

111 Normal data response

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