8050D N/B Maintenance

￿Block Locking Register for all blocks

￿Standard SDP Command Set

￿Data# Polling and Toggle Bit for End-of-Write detection

￿5 GPI pins for system design flexibility

￿4 ID pins for multi-chip selection

 

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1.3.11 Memory System

Secret

 

1.3.11.1 64MB, 128MB, 256MB,MiTac512MB (x64) 200-Pin DDR SDRAM SODIMM

￿ JEDEC-standardConfidential200-pin,small-outli e, dual in-line memory module (SODIMM) ￿ Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components

￿ 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg x 64 [HD])

￿ VDD= VDDQ= +2.5V ±0.2V

￿VDDSPD = +2.2V to +5.5V

￿2.5V I/O (SSTL_2 compatible)

￿Commands entered on each positive CK edge

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