8050D N/B Maintenance

5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(3)

PCI Interface Signals (Continued)

IDE Interface Signals (Continued)

Signal Name

Type

PME#

I/OD

CLKRUN# I/O

REQ[A]#/I GPIO[0]

REQ[B]#/

REQ[5]#/

GPIO[1]

GNT[A]#/O

GPIO[16]

GNT[B]#/

GNT[5]#/

GPIO[17]

IDE Interface Signals

Signal Name

Type

PDCS1#, SDCS1#

O

PDCS3#, SDCS3#

O

PDA[2:0],

O

SDA[2:0]

 

 

Description

 

 

Signal Name

Type

 

Description

PCI Power Management Event: PCI peripherals drive PME# to

 

 

PDD[15:0],

I/O

Primary and Secondary IDE Device Data: These signals directly

wake the system from low-power states S1-M–S5. PME# assertion

 

 

SDD[15:0]

 

drive the corresponding signals on the primary or secondary IDE

can also be enabled to generate an SCI from the S0 state. In some

 

 

 

 

connector. There is a weak internal pull-down resistor on PDD[7]

cases the ICH4 may drive PME# active due to an internal wake

 

 

 

 

and SDD[7].

event. The ICH4 will not drive PME# high, but it will be pulled up

 

 

PDDREQ,

I

Primary and Secondary IDE Device DMA Request: These input

to VccSus3_3 by an internal pull-up resistor.

 

 

SDDREQ

 

signals are directly driven from the DRQ signals on the primary or

PCI Clock Run: Used to support PCI Clock Run protocol.

 

 

 

 

secondary IDE connector. It is asserted by the IDE device to request

PC/PCI DMA Acknowledges [A: B]: This grant serializes n

 

Document

Connects to PCI devices that need to request clock re-start, or

 

 

 

 

a da a ransfer, and used in conjunction with the PCI bus master IDE

prevention of clock stopping.

Secret

 

func ion and are not associated with any AT compatible DMA

General Purpose Inputs. REQ[B]# can instead be used as the 6th

 

used in conjunction with the PCI bus master IDE function and are

NOTE: An external pull-up to the core power plane is required.

 

 

 

 

cha

el. There is a weak internal pull-down resistor on these

PC/PCI DMA Request [A:B]: This request serializes ISA-like

 

 

 

 

sig

als.

DMA Requests for the purpose of running ISA-compatible DMA

 

 

PDDACK#,

O

Primary and Secondary IDE Device DMA Acknowledge: These

cycles over the PCI bus. This is used by devices such as PCI based

 

 

SDDACK#

 

signals directly drive the DAK# signals on the primary and

Super I/O or audio codecs which need to perform legacy 8237 DMA

 

 

 

 

secondary IDE connectors. Each is asserted by the ICH4 to indicate

but have no ISA bus.

 

 

 

 

 

to IDE DMA slave devices that a given data transfer cycle (assertion

When not used for PC/PCI requests, these signals can be used as

 

 

 

 

of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is

but have no ISA bus.

MiTac

 

SDIOR#/

 

selected either by the ATA register file chip selects (PDCS1# or

PCI bus request.

 

 

 

P IOR#/

O

not associated with any AT-compatible DMA channel.

 

Confidential

(PDWSTB/PRDMA

 

DMA): This is the command to the IDE device that it may drive

ISA-like DACK# for the purpose of running DMA/ISA Master

 

 

 

cycles over the PCI bus. This is used by devices such as PCI based

 

 

RDY#)

 

data onto the PDD or SDD lines. Data is latched by the ICH4 on the

Super/IO or audio codecs which need to perform legacy 8237 DMA

 

 

 

 

deassertion edge of PDIOR# or SDIOR#. The IDE device is

When not used for PC/PCI, these signals can be us as Ge eral

 

 

(SDWSTB/SRDMA

 

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the

 

 

 

IDE DMA acknowledge (PDDAK# or SDDAK#).

Purpose Outputs. GNTB# can also be used as the 6th PCI bus

 

 

RDY#)

 

 

 

 

Primary and Secondary Disk Write Strobe (Ultra DMA Writes to

master grant output. These signal have internal pull-up resistors.

 

 

 

 

 

 

 

 

Disk): This is the data write strobe for writes to disk. When writing

 

 

 

 

 

 

 

 

 

 

 

 

to disk, ICH4 drives valid data on rising and falling edges of

 

 

 

 

 

 

PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready

 

Description

 

 

 

 

(Ultra DMA Reads from Disk): This is the DMA ready for reads

 

 

 

 

 

from disk. When reading from disk, ICH4 deasserts

Primary and Secondary IDE Device Chip Selects for 100 Range:

 

 

 

 

PRDMARDY# or SRDMARDY# to pause burst data transfers.

For ATA command register block. This output signal is connected

 

 

PDIOW#/

O

Primary and Secondary Disk I/O Write (PIO and Non-Ultra

to the corresponding signal on the primary or secondary IDE

 

 

(PDSTOP)

 

DMA): This is the command to the IDE device that it may latch

connector.

 

 

 

 

 

data from the PDD or SDD lines. Data is latched by the IDE device

Primary and Secondary IDE Device Chip Select for 300 Range:

 

 

SDIOW#/

 

on the deassertion edge of PDIOW# or SDIOW#. The IDE device is

For ATA control register block. This output signal is connected to

 

 

 

selected either by the ATA register file chip selects (PDCS1# or

 

 

(SDSTOP)

 

the corresponding signal on the primary or secondary IDE

 

 

 

SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the

 

 

 

 

connector.

 

 

 

 

 

IDE DMA acknowledge (PDDAK# or SDDAK#).

Primary and Secondary IDE Device Address: These output

 

 

 

 

Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this

signals are connected to the corresponding signals on the primary or

 

 

 

 

signal to terminate a burst.

secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed.

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