8050D N/B Maintenance

￿ 128 pin QFP/LQFP

￿ Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip ￿ 10 Mb/s and 100 Mb/s operation

￿ Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation ￿ PCI local bus single-chip Fast Ethernet controller

￿ Compliant to PCI Revision 2.2

 

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￿ Supports PCI clock 16.75MHz-40MHz

 

 

￿ Supports PCI target fast back-to-back transaction

MiTac

 

￿ Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of

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RTL8100C(L)'s operational registers

 

 

￿ Supports PCI VPD (Vital Product Data) ￿ Supports ACPI, PCI power management

￿ Supports 25MHz crystal or 25MHz OSC as the internal clock source.

￿ The frequency deviation of either crystal or OSC must be within 50 PPM.

￿ Compliant to PC99/PC2001 standard

￿ Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up frame)

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