During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The assertion of G_TRDY# indicates the target’s ability to complete the current data phase of the transaction.

8050D N/B Maintenance

5.2 Intel 855GM/GME North Bridge(6)

AGP/PCI Signals-Semantics Descriptions (Continued)

ATP/PCI Signals-Semantics Descriptions(Continued)

Signal Name

Type

Description

Signal Name

Type

Description

GTRDY#

I/O

G_TRDY#: Target Ready.

GGNT#

O

G_GNT#: Grant.

 

AGP

During PIPE# and SBA Operation: Not used while enqueueing

 

AGP

During SBA, PIPE# and FRAME# Operation: G_GNT#, along

 

 

requests via AGP SBA and PIPE#, but used during the data phase of

 

 

with the information on the ST[2:0] signals (status bus), indicates

 

 

PIPE# and SBA transactions.

 

 

how the AGP interface will be used next. Refer to the AGP Interface

 

 

 

 

 

Specification, Revision 2.0 for further explanation

 

 

 

 

 

of the ST[2:0] values and their meanings.

GSTOP#

I/O

 

AGP

GDEVSEL# I/O AGP

GREQ#

I

 

AGP

 

 

 

 

 

GAD[31:0]

I/O

G_AD[31:0]: Address/Data Bus.

 

 

 

 

 

 

AGP

During PIPE# and FRAME# Operation: The G_AD[31:0] signals

During Fast Write Operation: In Fast Write mode, G_TRDY#

 

 

 

 

are used o transfer both address and data information on the AGP

 

 

 

 

i terface.

indicates the AGP-compliant target is ready to receive write data for

 

 

 

 

Duri g SBA Operation: The G_AD[31:0] signals are used to

the entire transaction (when the transfer size is less than or equal to 32

 

 

 

 

transfer data on the AGP interface.

bytes) or is ready to transfer the initial or

 

 

 

GCBE#[3:0]

I/O

Command/Byte Enable.

subsequent block (32 bytes) of data when the transfer size is greater

Secret

AGP

During FRAME# Operation: During the address phase of a

than 32 bytes. The target is allowed to insert wait states after each

 

transaction, the G_CBE[3:0]# signals define the bus command.

block (32 bytes) is transferred on write transactions.

 

During the data phase, the G_CBE[3:0]# signals are used as byte

G_STOP#: Stop.

 

 

 

enables. The byte enables determine which byte lanes carry

During PIPE# and SBA Operation: This signal is not used during

 

 

 

 

meaningful data. The commands issued on the G_CBE# signals

PIPE# or SBA operation.

 

 

 

 

 

 

during FRAME#-based AGP transactions are the same G_CBE#

During FRAME# Operation: G STOP# is an input when the

 

Document

 

 

 

 

command described in the PCI 2.2 specification.

GMCH acts as a FRAME#-based AGP initiator and s an output when

 

 

 

 

During PIPE# Operation: When an address is enqueued using

the GMCH acts as a FRAME#-based AGP target. G STOP# is used

 

 

 

 

PIPE#, the C/BE# signals carry command information. The command

for disconnect, retry, and abort sequences on the AGP terface.

 

 

 

 

encoding used during PIPE#-based AGP is different than the

G_ DEVSEL#: Device Select.

MiTac

 

 

 

command encoding used during FRAME#-based AGP cycles (or

During PIPE# and SBA Operation: This signal is not us during

 

 

 

 

standard PCI cycles on a PCI bus).

PIPE# or SBA operation.

 

 

 

 

 

 

During SBA Operation: These signals are not used during SBA

During FRAME# Operation: G DEVSEL#, when asserted,

 

 

 

 

operation.

indicates that a FRAME#-based AGP target dev ce has decoded its

 

 

GPAR

I/O

Parity.

address as the target of the current access. The GMCH asserts

 

 

 

AGP

During FRAME# Operation: G_PAR is driven by the GMCH when

G_DEVSEL# based on the DDR SDRAM

 

 

 

 

 

it acts as a FRAME#-based AGP initiator during address and data

address range being accessed by a PCI initiator. As an input,

 

 

 

 

phases for a write cycle, and during the address phase for a read

G_DEVSEL# indicates whether the AGP master has recognized

 

 

 

 

cycle. G_PAR is driven by the GMCH when it acts as a

PCI cycle to it.

Confidential

 

 

FRAME#-based AGP target during each data phase of a

G_REQ#: Request.

 

 

 

 

 

 

FRAME#-based AGP memory read cycle. Even parity is generated

During SBA Operation: This signal is not used during SBA

 

 

 

 

across G_AD[31:0] and G_CBE[3:0]#.

operation.

 

 

 

 

 

 

During SBA and PIPE# Operation: This signal is not used during

During PIPE# and FRAME# Operation: G_REQ#, when asserted,

 

 

 

 

SBA and PIPE# operation.

indicates that the AGP master is requesting use of the AGP interface

 

 

PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface

to run a FRAME#- or PIPE#-based operation.

 

 

logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as

 

 

 

 

 

an input to reset its internal logic.

80