8170 N/B MAINTENANCE
5.1 Pentium 4(Willamette/Northwood)
Name | Type | Description |
BPM[5:0]# | Input/ | BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance |
| Output | monitor signals. They are outputs from the processor which indicate |
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| the status of breakpoints and programmable counters used for |
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| monitoring processor performance. BPM[5:0]# should connect the |
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| appropriate pins of all Pentium 4 processor in the |
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| system bus agents. |
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| BPM4# provides PRDY# (Probe Ready) functionality for the TAP |
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| port. PRDY# is a processor output used by debug tools to determine |
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| processor debug readiness. |
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| BPM5# provides PREQ# (Probe Request) functionality for the TAP |
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| port. PREQ# is used by debug tools to request debug operation of |
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| the processor. Please refer to the Intel® Pentium® 4 Processor in |
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| the |
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| Guide for more detailed information. |
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| These signals do not have |
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| Pentium® 4 Processor in the |
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| Chipset Platform Design Guide for termination requirements. |
BPRI# | Input | BPRI# (Bus Priority Request) is used to arbitrate for ownership of |
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| the processor system bus. It must connect the appropriate pins of all |
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| processor system bus agents. Observing BPRI# active (as asserted |
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| by the priority agent) causes all other agents to stop issuing new |
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| requests, unless such requests are part of an ongoing locked |
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| operation. The priority agent keeps BPRI# asserted until all of its |
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| requests are completed, then releases the bus by deasserting BPRI#. |
BR0# | Input/ | BR0# drives the BREQ0# signal in the system and is used by the |
| Output | processor to request the bus. During |
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| is sampled to determine the agent ID = 0. |
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| This signal does not have |
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| terminated. |
BSEL[1:0] | Output | The BCLK[1:0] frequency select signals BSEL[1:0] are used to |
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| select the processor input clock frequency. The required frequency |
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| is determined by the processor, chipset and clock synthesizer. All |
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| agents must operate at the same frequency. The Pentium 4 |
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| processor in the |
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| system bus frequency (100 MHz BCLK[1:0] frequency). For more |
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| information about these pins, including termination |
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| recommendations. |
COMP[1:0] | Analog | COMP[1:0] must be terminated on the system board using precision |
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| resistors. Refer to the Intel® Pentium® 4 Processor in the |
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| Package and Intel® 850 Chipset Platform Design Guide for details |
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| on implementation. |
Name | Type |
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D[63:0]# | Input/ | D[63:0]# (Data) are the data signals. These signals provide a | |||||||||
| Output | data path between the processor system bus agents, and must | |||||||||
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| connect the appropriate pins on all such agents. The data driver | |||||||||
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| asserts DRDY# to indicate a valid data transfer. | |||||||||
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| D[63:0]# are | |||||||||
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| times in a common clock period. D[63:0]# are latched off the falling | |||||||||
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| edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 | |||||||||
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| data signals correspond to a pair of one DSTBP# and one DSTBN#. | |||||||||
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| The following table shows the grouping of data signals to data | |||||||||
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| strobes and DBI#. |
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| Data Group |
| DSTBN#/ |
| DBI# |
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| DSTBP# |
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| D[15:0]# |
| 0 |
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| 0 |
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| D[31:16]# |
| 1 |
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| 1 |
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| D[47:32]# |
| 2 |
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| 2 |
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| D[63:48]# |
| 3 |
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| 3 |
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| Furthermore, the DBI# pins determine the polarity of the data | |||||||||
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| signals. Each group of 16 data signals corresponds to one DBI# | |||||||||
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| signal. When the DBI# signal is active, the corresponding data | |||||||||
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| group is inverted and therefore sampled active high. | |||||||||
DBI[3:0]# | Input/ | DBI[3:0]# are source synchronous and indicate the polarity of the | |||||||||
| Output | D[63:0]# signals. The DBI[3:0]# signals are activated when the data | |||||||||
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| on the data bus is inverted. The bus agent will invert the data bus | |||||||||
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| signals if more than half the bits, within the covered group, would | |||||||||
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| change level in the next cycle. |
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| DBI[3:0] Assignment To Data Bus |
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| Bus Signal |
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| Data Bus Signals |
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| DBI3# |
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| D[63:48]# |
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| DBI2# |
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| D[47:32]# |
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| DBI1# |
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| D[31:16]# |
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| DBI0# |
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| D[15:0]# |
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DBR# | Output | DBR# is used only in processor systems where no debug port is | |||||||||
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| implemented on the system board. DBR# is used by a debug port | |||||||||
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| interposer so that an | |||||||||
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| debug port is implemented in the system, DBR# is a no connect in | |||||||||
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| the system. DBR# is not a processor signal. | |||||||||
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