8170 N/B MAINTENANCE
5.4 PCI4410(PCMCIA/1394 LINK Controller )
Name | Type | Description |
REG# | O | Attribute memory select. REG# remains high for all common |
|
| memory accesses. When REG# is asserted, access is limited to |
|
| attribute memory (OE# or WE# active) and to the I/O space (IORD# |
|
| or IOWR# active). Attribute memory is a separately accessed section |
|
| of card memory and generally is used to record card capacity and |
|
| other configuration and attribute information. DMA acknowledge. |
|
| REG is used as a DMA acknowledge (DACK#) during DMA |
|
| operations to a |
|
| device asserts REG# to indicate a DMA operation. REG# is used in |
|
| conjunction with the DMA read (IOWR#) or DMA write (IORD#) |
|
| strobes to transfer data. |
RESET | O | PC Card reset. RESET forces a hard reset to a |
|
|
|
WAIT# | I | Bus cycle wait. WAIT# is driven by a |
|
| completion of the memory or I/O cycle in progress. |
WE# | O | Write enable. WE# is used to strobe memory write data into |
|
| memory PC Cards. WE# also is used for memory PC Cards that |
|
| employ programmable memory technologies. DMA terminal count. |
|
| WE# is used as TC during DMA operations to a |
|
| supports DMA. The PCI4410A device asserts WE to indicate TC for |
|
| a DMA read operation. |
WP | I | Write protect. WP applies to |
IOIS16# |
| the status of the |
|
| |
|
| function. I/O is 16 bits. IOIS16# applies to |
|
| IOIS16# is asserted by the |
|
| bus corresponds to an address to which the |
|
| and the I/O port that is addressed is capable of |
|
| DMA request. WP can be used as the DMA request signal during |
|
| DMA operations to a |
|
| PC Card asserts WP to indicate a request for a DMA operation. |
VS1# | I/O | Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in |
VS2# |
| conjunction with each other, determine the operating voltage of the |
|
| PC Card. |
CardBus PC Card Interface System Terminals
Name | Type | Description |
CCLK | O | CardBus clock. CCLK provides synchronous timing for all |
|
| transactions on the CardBus interface. All signals except CRST#, |
|
| CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#, |
|
| CVS2, and CVS1 are sampled on the rising edge of CCLK, and all |
|
| timing parameters are defined with the rising edge of this signal. |
|
| CCLK operates at the PCI bus clock frequency, but it can be stopped |
|
| in the low state or slowed down for power savings. |
CCLKRUN# | I/O | CardBus clock run. CCLKRUN# is used by a CardBus PC Card to |
|
| request an increase in the CCLK frequency, and by the PCI4410A |
|
| device to indicate that the CCLK frequency is going to be decreased. |
CRST# | O | CardBus reset. CRST# brings CardBus PC |
|
| sequencers, and signals to a known state. When CRST# is asserted, |
|
| all CardBus PC Card signals are placed in a |
|
| and the PCI4410A device drives these signals to a valid logic level. |
|
| Assertion can be asynchronous to CCLK, but deassertion must be |
|
| synchronous to CCLK. |
CardBus PC Card Address and Data Terminals
Name | Type | Description |
CAD[0:31] | I/O | CardBus address and data. These signals make up the multiplexed |
|
| CardBus address and data bus on the CardBus interface. During the |
|
| address phase of a CardBus cycle, |
|
| address. During the data phase of a CardBus cycle, |
|
| contain data. CAD31 is the most significant bit. |
CC/BE[0:3]# | I/O | CardBus bus commands and byte enables. |
|
| multiplexed on the same CardBus terminals. During the address phase |
|
| of a CardBus cycle, |
|
| During the data phase, this |
|
| enables determine which byte paths of the full |
|
| meaningful data. CC/BE0# applies to byte 0 |
|
| CC/BE1# applies to byte 1 |
|
| byte 2 |
|
| |
CPAR | I/O | CardBus parity. In all CardBus read and write cycles, the PCI4410A |
|
| device calculates even parity across the CAD and CC/BE buses. As |
|
| an initiator during CardBus cycles, the PCI4410A device outputs |
|
| CPAR with a |
|
| the calculated parity is compared to the initiator’s parity indicator; a |
|
| compare error results in a |
133