8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
PCI Interface Signals
Name | Type | Description |
PME# | I | PCI Power Management Event: PCI peripherals drive PME# to |
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| wake the system from |
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| also be enabled to generate SCI from the S0 state. In some cases the |
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| ICH2 may drive PME# active due to an internal wake event. The |
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| ICH2 will not drive PME# high, but it will be pulled up to VccSus3_3 |
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| by an internal |
CLKRUN# | I/O | PCI Clock Run: For the |
| Clock Run protocol. This signal connects to PCI devices that need to | |
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| request clock |
REQ[A]# / | I | PC/PCI DMA Request [A:B]: This request serializes |
GPIO[0] |
| Requests for the purpose of running |
REQ[B]# / |
| over the PCI bus. This is used by devices such as |
REQ[5]# / |
| I/O or audio codecs that need to perform legacy 8237 DMA but have |
GPIO[1] |
| no ISA bus. |
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| When not used for PC/PCI requests, these signals can be used as |
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| General Purpose Inputs. Instead, REQ[B]# can be used as the 6th PCI |
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| bus request. |
GNT[A]# / | O | PC/PCI DMA Acknowledges [A:B]: This grant serializes an |
GPIO[16] |
| |
GNT[B]# / |
| over the PCI bus. This is used by devices such as |
GNT[5]# / |
| or audio codecs which need to perform legacy 8237 DMA but have |
GPIO[17] |
| no ISA bus. |
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| When not used for PC/PCI, these signals can be used as General |
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| Purpose Outputs. GNTB# can also be used as the 6th PCI bus master |
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| grant output. These signal have internal |
IDE Interface Signals
Name | Type | Description |
PDCS1#, | O | Primary and Secondary IDE Device Chip Selects for 100 Range: |
SDCS1# |
| These signals are for the ATA command register block. This output |
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| signal is connected to the corresponding signal on the primary or |
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| secondary IDE connector. |
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PDCS3#, | O | Primary and Secondary IDE Device Chip Select for 300 Range: |
SDCS3# |
| These signals are for the ATA control register block. This output |
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| signal is connected to the corresponding signal on the primary or |
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| secondary IDE connector. |
IDE Interface Signals(continued)
Name | Type | Description |
PDA[2:0], | O | Primary and Secondary IDE Device Address: These output signals |
SDA[2:0] |
| are connected to the corresponding signals on the primary or |
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| secondary IDE connectors. They are used to indicate which byte in |
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| either the ATA command block or control block is being addressed. |
PDD[15:0], | I/O | Primary and Secondary IDE Device Data: These signals directly |
SDD[15:0] |
| drive the corresponding signals on the primary or secondary IDE |
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| connector. There is a weak internal |
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| SDD[7]. |
PDDREQ, | I | Primary and Secondary IDE Device DMA Request: These input |
SDDREQ |
| signals are directly driven from the DRQ signals on the primary or |
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| secondary IDE connector. It is asserted by the IDE device to request a |
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| data transfer, and used in conjunction with the PCI bus master IDE |
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| function. They are not associated with |
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| any |
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| |
PDDACK#, | O | Primary and Secondary IDE Device DMA Acknowledge: These |
SDDACK# |
| signals directly drive the DAK# signals on the primary and secondary |
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| IDE connectors. Each signal is asserted by the ICH2 to indicate to the |
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| IDE DMA slave devices that a given data transfer cycle (assertion of |
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| DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used |
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| in conjunction with the PCI bus master IDE function and are not |
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| associated with any |
PDIOR# | O | Primary and Secondary Disk I/O Read (PIO and |
SDIOR# |
| DMA): This is the command to the IDE device that it may drive data |
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| on the PDD or SDD lines. Data is latched by the ICH2 on the |
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| deassertion edge of PDIOR# or SDIOR#. The IDE device is selected |
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| either by the ATA register file chip selects (PDCS1# or SDCS1#, |
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| PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA |
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| acknowledge (PDDAK# or SDDAK#). |
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| Primary and Secondary Disk Write Strobe (Ultra DMA Writes to |
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| Disk): This is the data write strobe for writes to disk. When writing to |
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| disk, ICH2 drives valid data on rising and falling edges of PDWSTB |
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| or SDWSTB. |
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| Primary and Secondary Disk DMA Ready (Ultra DMA Reads |
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| from Disk): This is the DMA ready for reads from disk. When |
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| reading from disk, ICH2 deasserts PRDMARDY# orSRDMARDY# |
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| to pause burst data transfers. |
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