8170 N/B MAINTENANCE
5.4 PCI4410(PCMCIA/1394 LINK Controller )
Name | Type | Description |
ADDR[0:25] | O | PC Card address. |
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| significant bit |
DATA[0:15] | I/O | PC Card data. |
|
| significant bit. |
Name | Type | Description |
BVD1 | I | Battery voltage detect 1. BVD1 is generated by |
(STSCHG#/RI#) |
| Cards that include batteries. BVD1 is used with BVD2 as an |
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| indication of the condition of the batteries on a memory PC Card. |
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| Both BVD1 and BVD2 are high when the battery is good. When |
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| BVD2 is low and BVD1 is high, the battery is weak |
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| and should be replaced. When BVD1 is low, the battery is no longer |
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| serviceable and the data in the memory PC Card is lost. See Section |
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| 5.6, ExCA Card |
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| enable bits. See Section 5.5, ExCA Card |
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| Section 5.2,ExCA Interface Status Register, for the status bits for this |
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| signal. Status change. STSCHG# is used to alert the system to a |
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| change in the READY, write protect, or battery voltage dead |
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| condition of a |
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| modem cards to indicate a ring detection. |
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BVD2 | I | Battery voltage detect 2. BVD2 is generated by |
(SPKR#) |
| Cards that include batteries. BVD2is used with BVD1 as an |
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| indication of the condition of the batteries on a memory PC Card. |
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| Both BVD1and BVD2 are high when the battery is good. When |
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| BVD2 is low and BVD1 is high, the battery is weak and should be |
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| replaced. When BVD1 is low, the battery is no longer serviceable and |
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| the data in the memory PC Card is lost. See Section 5.6, ExCA Card |
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| |
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| Section 5.5, ExCA Card |
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| ExCA Interface Status Register, for the status bits for this signal. |
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| Speaker. SPKR# is an optional binary audio signal available only |
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| when the card and socket have been configured for the |
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| interface. The audio signals from cards A and B are combined by the |
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| PCI4410A device and are output on SPKROUT.DMA request. BVD2 |
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| can be used as the DMA request signal during DMA operations to a |
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| |
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| indicate a request for a DMA operation. |
CD1# | I | Card detect 1 and Card detect 2. CD1# and CD2# are connected |
CD2# |
| internally to ground on the PC Card. When a PC Card is inserted into |
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| a socket, CD1# and CD2# are pulled low. For signal status, see |
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| Section 5.2, ExCA Interface Status Register. |
Name | Type | Description |
CE1# | O | Card enable 1 and card enable 2. CE1# and CE2# enable even- and |
CE2# |
| |
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| bytes, and CE2# enables |
INPACK# | I | Input acknowledge. INPACK# is asserted by the PC Card when it |
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| can respond to an I/O read cycle at the current address.DMA request. |
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| INPACK# can be used as the DMA request signal during DMA |
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| operations from a |
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| strobe, the PC Card asserts this signal to indicate a request for a DMA |
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| operation. |
IORD# | O | I/O read. IORD# is asserted by the PCI4410A device to enable |
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| I/O PC Card data output during host I/O read cycles. DMA write. |
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| IORD# is used as the DMA write strobe during DMA operations from |
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| a |
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| IORD# during DMA transfers from the PC Card to host memory. |
IOWR# | O | I/O write. IOWR# is driven low by the PCI4410A device to strobe |
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| write data into |
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| DMA read. IOWR# is used as the DMA write strobe during DMA |
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| operations from a |
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| device asserts IOWR during transfers from host memory to the PC |
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| Card. |
OE# | O | Output enable. OE# is driven low by the PCI4410A device to enable |
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| |
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| DMA terminal count. OE# is used as terminal count (TC) during |
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| DMA operations to a |
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| PCI4410A device asserts OE# to indicate TC for a DMA write |
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| operation. |
READ | I | Ready. The ready function is provided by READY when the |
IREQ# |
| PC Card and the host socket are configured for the |
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| interface. READY is driven low by the |
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| indicatethat the memory card circuits are busy processing a previous |
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| write command. READY is driven high when the |
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| Card is ready to accept a new |
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| request. IREQ# is asserted by a |
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| host that a device on the |
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| host software. IREQ# is high (deasserted) when no interrupt is |
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| requested. |
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