8170 N/B MAINTENANCE
5.Pin Descriptions of Major Components
5.1Pentium 4(Willamette/Northwood)
Name | Type |
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A[35:3]# | Input/ | A[35:3]# (Address) define a 2 36 | ||||
| Output | space. In | ||||
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| address of a transaction. In | ||||
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| transaction type information. These signals | ||||
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| must connect the appropriate pins of all agents on the Pentium 4 | ||||
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| processor in the | ||||
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| protected by parity signals AP[1:0]#. A[35:3]# are source | ||||
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| synchronous signals and are latched into the receiving buffers by | ||||
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| ADSTB[1:0]#. On the | ||||
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| processor samples a subset of the A[35:3]# pins to determine | ||||
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A20M# | Input | If A20M# | ||||
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| physical address bit 20 (A20#) before looking up a line in any | ||||
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| internal cache and before driving a read/write transaction on the | ||||
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| bus. Asserting A20M# emulates the 8086 processor's address | ||||
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| supported in real mode. |
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| A20M# is an asynchronous signal. However, to ensure recognition | ||||
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| of this signal following an Input/Output write instruction, it must be | ||||
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| valid along with the TRDY# assertion of the corresponding | ||||
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| Input/Output Write bus transaction. | ||||
ADS# | Input/ | ADS# (Address Strobe) is asserted to indicate the validity of the | ||||
| Output | transaction address on the A[35:3]# and REQ[4:0]# pins. All bus | ||||
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| agents observe the ADS# activation to begin parity checking, | ||||
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| protocol checking, address decode, internal snoop, or deferred reply | ||||
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| ID match operations associated with the new transaction. | ||||
ADSTB[1:0]# | Input/ | Address strobes are used to latch A[35:3]# and REQ[4:0]# on their | ||||
| Output | rising and falling edges. Strobes are associated with signals as | ||||
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| Associated Strobe |
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| REQ[4:0]#, A[16:3]# |
| ADSTB0# |
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| A[35:17]# |
| ADSTB1# |
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Name | Type |
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| Description |
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AP[1:0]# | Input/ | AP[1:0]# (Address Parity) are driven by the request initiator along | ||||||
| Output | with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A | ||||||
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| correct parity signal is high if an even number of covered signals | ||||||
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| are low and low if an odd number of covered signals are low. This | ||||||
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| allows parity to be high when all the covered signals are high. | ||||||
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| AP[1:0]# should connect the appropriate pins of all Pentium 4 | ||||||
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| processor in the | ||||||
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| table defines |
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| Request Signals | subphase 1 |
| subphase 2 |
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| A[35:24]# | AP0# |
| AP1# |
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| A[23:3]# | AP1# |
| AP0# |
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| REQ[4:0]# | AP1# |
| AP0# |
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BCLK[1:0] | Input | The differential pair BCLK (Bus Clock) determines the system bus | ||||||
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| frequency. All processor system bus agents must receive these | ||||||
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| signals to drive their outputs and latch their inputs. |
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| All external timing parameters are specified with respect to the | ||||||
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| rising edge of BCLK0 crossing V CROSS . |
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BINIT# | Input/ | BINIT# (Bus Initialization) may be observed and driven by all | ||||||
| Output | processor system bus agents and if used, must connect the | ||||||
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| appropriate pins of all such agents. If the BINIT# driver is enabled | ||||||
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| during |
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| to signal any bus condition that prevents reliable future operation. | ||||||
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| If BINIT# observation is enabled during | ||||||
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| and BINIT# is sampled asserted, symmetric agents reset their bus | ||||||
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| LOCK# activity and bus request arbitration state machines. The bus | ||||||
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| agents do not reset their IOQ and transaction tracking state | ||||||
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| machines upon observation of BINIT# activation. Once the BINIT# | ||||||
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| assertion has been observed, the bus agents will | ||||||
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| system bus and attempt completion of their bus queue and IOQ | ||||||
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| entries. |
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| If BINIT# observation is disabled during | ||||||
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| central agent may handle an assertion of BINIT# as appropriate to | ||||||
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| the error handling architecture of the system. |
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BNR# | Input/ | BNR# (Block Next Request) is used to assert a bus stall by any bus | ||||||
agent who is unable to accept new bus transactions. During a bus | ||||||||
Output | ||||||||
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| stall, the current bus owner cannot issue any new transactions. |
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