8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
Power Management Interface Signals
Name | Type | Description |
THRM# | I | Thermal Alarm: THRM# is an active low signal generated by |
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| external hardware to start the hardware clock throttling mode. This |
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| signal can also generate an SMI# or an SCI. |
SLP_S1# | O | S1 Sleep Control: Clock synthesizer or power plane control. This |
| signal connects to clock synthesizer’s PWRDWN# signal. An | |
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| optional use is to shut off power to |
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| S1 (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to |
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| Disk), or S5 (Soft Off) states. |
SLP_S3# | O | S3 Sleep Control: Power plane control. This signal is used to shut off |
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| power to all |
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| (Suspend to Disk) or S5 (Soft Off) states. |
SLP_S5# | O | S5 Sleep Control: Power plane control. This signal is used to shut |
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| power off to all |
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| Disk) or S5 (Soft Off) states. |
PWROK | I | Power OK: When asserted, PWROK is an indication to the ICH2 |
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| that core power and PCICLK have been stable for at least 1 ms. |
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| PWROK can be driven asynchronously. When PWROK is negated, |
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| the ICH2 asserts PCIRST#. |
RSM_PWROK | I | Resume Well Power OK: When asserted, this signal is an indication |
(ICH2 0nly) |
| to the ICH2 that the resume well power (VccSus3_3, VccSus1_8) has |
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| been stable for at least10 ms. |
LAN_PWROK | I | LAN Power OK: When asserted, this signal is an indication to the |
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| has been stable for at least 10 ms. |
PWRBTN# | I | Power Button: The Power Button will cause SMI# or SCI to indicate |
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| a system request to go to a sleep state. If the system is already in a |
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| sleep state, this signal will cause a wake event. If PWRBTN# is |
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| pressed for more than 4 seconds, this will cause an unconditional |
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| transition (power button override) to the S5 state with only the |
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| PWRBTN# available as a wake event. Override will occur even if the |
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| system is in the |
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| resistor. |
RI# | I | Ring Indicate: From the modem interface. This signal can be enabled |
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| as a wake event; this is preserved across power failures. |
RSMRST# | I | Resume Well Reset: RSMRST# is used for resetting the resume |
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| power plane logic. |
SUS_STAT# / | O | Suspend Status: This signal is asserted by the ICH2 to indicate that |
LPCPD# |
| the system will be entering a low power state soon. This can be |
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| monitored by devices with memory that need to switch from normal |
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| refresh to suspend refresh mode. It can also be used by other |
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| peripherals as an indication that they should isolate their outputs that |
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| may be going to |
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| the LPC interface. |
Name | Type | Description |
C3_STAT# / | O | C3_STAT#: This |
GPIO[21] |
| C3_STAT#. It is used for indicating to an AGP device that a C3 state |
| transition is beginning or ending. If C3_STAT# functionality is not | |
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| required, this signal can be used as a GPO. |
SUSCLK | O | Suspend Clock: This signal is an output of the RTC generator circuit |
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| and is used by other chips for the refresh clock. |
VRMPWRGD | I | VRM Power Good (ICH2 and |
(ICH2) |
| connected to be the processor’s VRM Power Good. |
VRMPWRGD/ |
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VGATE |
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VGATE / | I | VRM Power Good Gate |
VRMPWRGD |
| SpeedStepTM technology support. It is an output from the |
| processor’s voltage regulator to indicate that the voltage is stable. | |
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| This signal can go inactive during a Intel® SpeedStepTM transition. |
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| In |
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| signal should be connected to the processor VRM Power Good. |
AGPBUSY# | I | AGP Bus Busy: This signal supports the C3 state. It provides an |
| indication that the AGP device is busy. When this signal is asserted, | |
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| the BM_STS bit will be set. If this functionality is not needed, this |
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| signal may be configured as a GPI. |
STP_PCI# | O | Stop PCI Clock: This signal is an output to the external clock |
| generator to turn off the PCI clock. It is used to support PCI | |
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| CLKRUN# protocol. If this functionality is not needed, this signal |
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| can be configured as a GPO. |
STP_CPU# | O | Stop CPU Clock: Output to the external clock generator to turn off |
| the processor clock. It is used to support the C3 state. If this | |
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| functionality is not needed, this signal can be configured as a GPO. |
BATLOW# | I | Battery Low: Input from battery to indicate that there is insufficient |
| power to boot the system. Assertion prevents wake from | |
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| This signal can also be enabled to cause an SMI# when asserted. In |
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| desktop configurations this signal should be pulled high to VccSUS. |
CPUPERF# | OD | CPU Performance: This signal is used for Intel® SpeedStepTM |
| technology support. It selects which power state to put the processo | |
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| in. If this functionality is not needed, this signal can be configured as |
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| a GPO. This is an |
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SSMUXSEL | O | SpeedStep Mux Select: This signal is used for Intel SpeedStepTM |
| technology support. It selects the voltage level for the processor. If | |
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| this functionality is not needed, this signal can be configured as a |
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| GPO. |
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