8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
PCI Interface Signals
Name | Type | Description |
FRAME# | I/O | Cycle Frame: The current Initiator drives FRAME# to indicate the |
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| beginning and duration of a PCI transaction. While the initiator |
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| asserts FRAME#, data transfers continue. When the initiator negates |
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| FRAME#, the transaction is in the final data phase. FRAME# is an |
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| input to the ICH2 when the ICH2 is the target, and FRAME# is an |
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| output from the ICH2 when the ICH2 is the Initiator. FRAME# |
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| remains |
IRDY# | I/O | Initiator Ready: IRDY# indicates the ICH2's ability, as an Initiator, |
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| to complete the current data phase of the transaction. It is used in |
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| conjunction with TRDY#. A data phase is completed on any clock |
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| both IRDY# and TRDY# are sampled asserted. During a write, |
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| IRDY# indicates the ICH2 has valid data present on AD[31:0]. |
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| During a read, it indicates the ICH2 is prepared to latch data. IRDY# |
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| is an input to the ICH2 when the ICH2 is the Target and an output |
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| from the ICH2 when the ICH2 is an Initiator. IRDY# remains |
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| |
TRDY# | I/O | Target Ready: TRDY# indicates the ICH2's ability as a Target to |
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| complete the current data phase of the transaction. TRDY# is used in |
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| conjunction with IRDY#. A data phase is completed when both |
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| TRDY# and IRDY# are sampled asserted. During a read, TRDY# |
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| indicates that the ICH2, as a Target, has placed valid data on |
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| AD[31:0]. During a write, TRDY# indicates the ICH2, as a Target is |
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| prepared to latch data. TRDY# is an input to the ICH2 when the ICH2 |
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| is the Initiator and an output from the ICH2 when the ICH2 is a |
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| Target. TRDY# is |
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| TRDY# remains |
STOP# | I/O | Stop: STOP# indicates that the ICH2, as a Target, is requesting the |
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| Initiator to stop the current transaction. STOP# causes the ICH2, as an |
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| Initiatior, to stop the current transaction. STOP# is an output when the |
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| ICH2 is a target and an input when the ICH2 is an Initiator. STOP# is |
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REQ[0:4]# | I | PCI Requests: The ICH2 supports up to 6 masters on the PCI bus. |
REQ[5]# / |
| REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the |
REQ[B]# / |
| other, but not both). If not used for PCI or PC/PCI, |
GPIO[1] |
| REQ[5]#/REQ[B]# can instead be used as GPIO[1]. |
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| Note: REQ[0]# is programmable to have improved arbitration latency |
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| for supporting |
Name | Type | Description |
PAR | I/O | Calculated/Checked Parity: PAR uses "even" parity calculated on |
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| 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the |
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| ICH2 counts the number of 1s within the 36 bits plus PAR and the |
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| sum is always even. The ICH2 always calculates PAR on 36 bits, |
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| regardless of the valid byte enables. The ICH2 generates PAR for |
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| address and data phases and only guarantees PAR to be valid one PCI |
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| clock after the corresponding address or data phase. The ICH2 drives |
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| and |
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| ICH2 delays PAR by exactly one PCI clock. PAR is an output during |
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| the address phase (delayed one clock) for all ICH2 initiated |
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| transactions. PAR is an output during the data phase (delayed one |
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| clock) when the ICH2 is the Initiator of a PCI write transaction, and |
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| when it is the target of a read transaction. ICH2 checks parity when it |
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| is the target of a PCI write transaction. If a parity error is detected, the |
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| ICH2 sets the appropriate internal status bits, and has the option to |
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| generate an NMI# or SMI#. |
PERR# | I/O | Parity Error: An external PCI device drives PERR# when it receives |
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| data that has a parity error. The ICH2 drives PERR# when it detects a |
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| parity error. The ICH can either generate an NMI# or SMI# upon |
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| detecting a parity error (either detected internally or reported via the |
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| PERR# signal). |
GNT[0:4]# | O | PCI Grants: The ICH2 supports up to 6 masters on the PCI bus. |
GNT[5]# / |
| GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the |
GNT[B]# / |
| other, but not both). If not needed PCI or PC/PCI, GNT[5]# can |
GPIO[17]# |
| instead be used as a GPIO. |
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| |
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| they should be tied to the Vcc3_3 power rail. |
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| GNT[B]#/GNT[5]#/GPIO[17] has an internal pullup. |
PCICLK | I | PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all |
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| transactions on the PCI Bus. . |
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| Note:For 82801BAM |
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| STP_PCI# signal. The PCI Clock only stops based on SLP_S1# or |
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| SLP_S3#. |
PCIRST# | O | PCI Reset: ICH2 asserts PCIRST# to reset devices that reside on the |
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| PCI bus. The ICH2 asserts PCIRST# during |
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| initiates a hard reset sequence through the RC (CF9h) register. The |
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| ICH2 drives PCIRST# inactive a minimum of 1 ms after PWROK is |
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| driven active. The ICH2 drives PCIRST# active a minimum of 1 ms |
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| when initiated through the RC register. |
SERR# | I | System Error: SERR# can be pulsed active by any PCI device that |
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| detects a system error condition. Upon sampling SERR# active, the |
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| ICH2 has the ability to generate an NMI, SMI#, or interrupt. |
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