8170 N/B MAINTENANCE
5.1 Pentium 4(Willamette/Northwood)
Name | Type |
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| Description | ||
DBSY# | Input/ | DBSY# (Data Bus Busy) is asserted by the agent responsible for | ||||
| Output | driving data on the processor system bus to indicate that the data | ||||
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| bus is in use. The data bus isreleased after DBSY# is deasserted. | ||||
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| This signal must connect the appropriate pins on all processor | ||||
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| system bus agents. |
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DEFER# | Input | DEFER# is asserted by an agent to indicate that a transaction | ||||
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| cannot be guaranteed | ||||
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| DEFER# is normally the responsibility of the addressed | ||||
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| memory or Input/Output agent. This signal must connect the | ||||
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| appropriate pins of all processor system bus agents. | ||||
DP[3:0]# | Input/ | DP[3:0]# (Data parity) provide parity protection for the | ||||
| Output | D[63:0]# signals. They are driven by the agent responsible for | ||||
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| driving D[63:0]#, and must connect the appropriate pins of all | ||||
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| Pentium 4 processor in the | ||||
DSTBN[3:0]# | Input/ | Data strobe used to latch in D[63:0]#. | ||||
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| Signals |
| Associated Strobe |
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| D[15:0]#, DBI0# |
| DSTBN0# |
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| D[31:16]#, DBI1# |
| DSTBN1# |
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| D[47:32]#, DBI2# |
| DSTBN2# |
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| D[63:48]#, DBI3# |
| DSTBN3# |
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DSTBP[3:0]# | Input/ | Data strobe used to latch in D[63:0]#. | ||||
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| Signals |
| Associated Strobe |
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| D[15:0]#, DBI0# |
| DSTBP0# |
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| D[31:16]#, DBI1# |
| DSTBP1# |
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| D[47:32]#, DBI2# |
| DSTBP2# |
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| D[63:48]#, DBI3# |
| DSTBP3# |
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FERR# | Output | FERR# | ||||
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| detects an unmasked | ||||
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| the ERROR# signal on the Intel 387 coprocessor, and is | ||||
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| included for compatibility with systems using | ||||
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GTLREF | Input | GTLREF determines the signal reference level for AGTL+ input | ||||
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| pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the | ||||
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| AGTL+ receivers to determine if a signal is a logical 0 or | ||||
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| logical 1. Refer to the Intel® Pentium® 4 Processor in the | ||||
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| Guide for more information. |
Name | Type | Description |
HIT# | Input/ | HIT# (Snoop Hit) and HITM# (Hit Modified) convey |
HITM# | Output | transaction snoop operation results. Any system bus agent may |
| Input/ | assert both HIT# and HITM# together to indicate that it requires |
| a snoop stall, which can be continued by reasserting | |
| Output | HIT# and HITM# together. |
IERR# | Output | IERR# (Internal Error) is asserted by a processor as the result of |
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| an internal error. Assertion of IERR# is usually accompanied by |
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| a SHUTDOWN transaction on the processor system bus. This |
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| transaction may optionally be converted to an external error |
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| signal (e.g., NMI) by system core logic. The processor will keep |
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| IERR# asserted until the assertion of RESET#, BINIT#, or |
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| INIT#. |
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| This signals does not have |
IGNNE# | Input | IGNNE# (Ignore Numeric Error) is asserted to force the |
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| processor to ignore a numeric error and continue to execute |
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| noncontrol |
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| the processor generates an exception on a noncontrol |
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| caused an error.IGNNE# has no effect when the NE bit in |
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| control register 0 (CR0) is set. IGNNE# is an asynchronous |
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| signal. However, to ensure recognition of this signal following |
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| an Input/Output write instruction, it must be valid along with the |
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| TRDY# assertion of the corresponding Input/Output Write bus |
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| transaction. |
INIT# | Input | INIT# (Initialization), when asserted, resets integer registers |
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| inside the processor without affecting its internal caches or |
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| the |
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| configuration. The processor continues to handle snoop requests |
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| during INIT# assertion. INIT# is an asynchronous signal and |
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| must connect the appropriate pins of all processor system bus |
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| agents. If INIT# is sampled active on the active to inactive |
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| transition of RESET#, then the processor executes its |
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ITPCLKOUT[1:0] | Output | The ITPCLKOUT[1:0] pins do not provide any output for the |
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| Pentium® 4 processor in the |
ITP_CLK[1:0] | Input | ITP_CLK[1:0] are copies of BCLK that are used only in |
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| processor systems where no debug port is implemented on the |
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| system board. ITP_CLK[1:0] are used as BCLK[1:0] references |
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| for a debug port implemented on an interposer. If a debug port |
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| is implemented in the system, ITP_CLK[1:0] are no connects in |
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| the system. These are not processor signals. |
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