8170 N/B MAINTENANCE
5.2 Intel 82845(Brookdale Memory Controller HUB)
Hub Interface Signals
Name | Type | Description |
HI_[10:0] | I/O | Hub Interface Signals: Signals used for the hub interface. |
| CMOS |
|
HI_STB | I/O | Hub Interface Strobe: One of two differential strobe signals used to |
| CMOS | transmit or receive packet data over the hub interface. |
HI_STB# | I/O | Hub Interface Strobe Compliment: One of two differential strobe |
| CMOS | signals used to transmit or receive packet data over the hub interface. |
AGP Addressing Signals
Name | Type | Description |
PIPE# | I | Pipelined Read: This signal is asserted by the AGP master to |
| AGP | indicate a |
|
| the AD bus. One address is placed in the AGP request queue on each |
|
| rising clock edge while PIPE# is asserted. When PIPE# is deasserted, |
|
| no new requests are queued across the AD bus. |
|
| During SBA Operation: Not Used. |
|
| During FRAME# Operation: Not Used. |
|
| PIPE# is a sustained |
|
| controller), and is an MCH input. |
|
| Note: Initial AGP designs may not use PIPE# (i.e., PCI only 66 |
|
| MHz). Therefore, an 8 k. |
|
| required on the motherboard. |
SBA[7:0] | I | Sideband Address: These signals are used by the AGP master |
| AGP | (graphics controller) to place addresses into the AGP request queue. |
|
| The SBA bus and AD bus operate independently. That is, a |
|
| transaction can proceed on the SBA bus and the AD bus |
|
| simultaneously. |
|
| During PIPE# Operation: Not Used. |
|
| During FRAME# Operation: Not Used. |
|
| Note: When sideband addressing is disabled, these signals are |
|
| isolated (no external/internal |
AGP Flow Control Signals
Name | Type | Description |
RBF# | I | Read Buffer Full: RBF# indicates if the master is ready to accept |
| AGP | previously requested low priority read data. When RBF# is asserted, |
|
| the MCH is not allowed to initiate the return low priority read data. |
|
| That is, the MCH can finish returning the data for the request |
|
| currently being serviced. RBF# is only sampled at the beginning of a |
|
| cycle. If the AGP master is always ready to accept return read data, |
|
| then it is not required to implement this signal. |
|
| During FRAME# Operation: Not Used. |
WBF# | I | |
| AGP | write data from the MCH. When WBF# is asserted, the MCH is not |
|
| allowed drive fast write data to the AGP master. WBF# is only |
|
| sampled at the beginning of a cycle. If the AGP master is always |
|
| ready to accept fast write data, then it is not required to implement |
|
| this signal. |
|
| During FRAME# Operation: Not Used. |
AGP Status Signals
Name | Type | Description |
ST[2:0] | O | Status: ST[2:0] provides information from the arbiter to an AGP |
| AGP | Master on what it may do. ST[2:0] only have meaning to the master |
|
| when its G_GNT# is asserted. When G_GNT# is deasserted, these |
|
| signals have no meaning and must be ignored. Refer to the AGP |
|
| Interface Specification, Revision 2.0 for further explanation of the |
|
| ST[2:0] values and their meanings. |
|
| During FRAME# Operation: These signals are not used during |
|
| |
|
| master may begin a FRAME# transaction. |
NOTE: The above table contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset.
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