8170 N/B MAINTENANCE

5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin

Name

Type

Description

REQ[4:0]#

Input/

REQ[4:0]# (Request Command) must connect the appropriate

 

Output

pins of all processor system bus agents. They are asserted by the

 

 

current bus owner to define the currently active transaction type.

 

 

These signals are source synchronous to ADSTB0#. Refer to the

 

 

AP[1:0]# signal description for a details on parity checking of

 

 

these signals.

SKTOCC#

Output

SKTOCC# (Socket Occupied) will be pulled to ground by the

 

 

processor. System board designers may use this pin to determine

 

 

if the processor is present.

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the

 

 

processor to enter the Sleep state. During Sleep state, the

 

 

processor stops providing internal clock signals to all units,

 

 

leaving only the Phase-Locked Loop (PLL) still operating.

 

 

Processors in this state will not recognize snoops or interrupts.

 

 

The processor will recognize only assertion of the RESET#

 

 

signal, deassertion of SLP#, and removal of the BCLK input

 

 

while in Sleep state. If SLP# is deasserted, the processor exits

 

 

Sleep state and returns to Stop-Grant state, restarting its internal

 

 

clock signals to the bus and processor core units. If the BCLK

 

 

input is stopped while in the Sleep state the processor will exit

 

 

the Sleep state and transition to the Deep Sleep state.

SMI#

Input

SMI# (System Management Interrupt) is asserted

 

 

asynchronously by system logic. On accepting a System

 

 

Management Interrupt, the processor saves the current state and

 

 

enter System Management Mode (SMM). An SMI

 

 

Acknowledge transaction is issued, and the processor begins

 

 

program execution from the SMM handler.

 

 

If SMI# is asserted during the deassertion of RESET# the

 

 

processor will tristate its outputs.

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to

 

 

enter a low power Stop-Grant state. The processor issues a

 

 

Stop-Grant Acknowledge transaction, and stops providing

 

 

internal clock signals to all processor core units except the

 

 

system bus and APIC units. The processor continues to snoop

 

 

bus transactions and service interrupts while in Stop-Grant state.

 

 

When STPCLK# is deasserted, the processor restarts its internal

 

 

clock to all units and resumes execution. The assertion of

 

 

STPCLK# has no effect on the bus clock; STPCLK# is an

 

 

asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor

 

 

Test Bus (also knownas the Test Access Port).

Name

Type

Description

TDI

Input

TDI (Test Data In) transfers serial test data into the processor.

 

 

TDI provides the serial input needed for JTAG specification

 

 

support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the

 

 

processor. TDO provides the serial output needed for JTAG

 

 

specification support.

TESTHI[12:8]

Input

TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC

TESTHI[5:0]

 

power source through a resistor for proper processor operation.

 

 

 

THERMDA

Other

Thermal Diode Anode.

 

 

 

THERMDC

Other

Thermal Diode Cathode.

THERMTRIP#

Output

Assertion of THERMTRIP# (Thermal Trip) indicates the

 

 

processor junction temperature has reached a level beyond

 

 

which permanent silicon damage may occur. Measurement of

 

 

the temperature is accomplished through an internal thermal

 

 

sensor which is configured to trip at approximately 135°C.Upon

 

 

assertion of THERMTRIP#, the processor will shut off its

 

 

internal clocks (thus halting program execution) in an attempt to

 

 

reduce the processor junction temperature. To protect the

 

 

processor, its core voltage (VCC) must be removed following

 

 

the assertion of THERMTRIP#. Once activated,

 

 

THERMTRIP# remains latched until RESET# is asserted.

 

 

While the assertion of the RESET# signal will de-assert

 

 

THERMTRIP# , if the processor’s junction

 

 

temperature remains at or above the trip level, THERMTRIP#

 

 

will again be asserted after RESET# is de-asserted.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal

 

 

used by debug tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that

 

 

it is ready to receive a write or implicit writeback data transfer.

 

 

TRDY# must connect the appropriate pins of all system bus

 

 

agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic.

 

 

TRST# must be driven low during power on Reset. This can be

 

 

done with a 680 . pull-down resistor.

VCCA

Input

VCCA provides isolated power for the internal processor core

 

 

PLLs. Refer to the Intel® Pentium® 4 Processor in the 478-pin

 

 

Package and Intel® 850 Chipset Platform Design Guide for

 

 

complete implementation details.

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