8170 N/B MAINTENANCE

5.4 PCI4410(PCMCIA/1394 LINK Controller )

CardBus PC Card Interface Control Terminals

Name

Type

Description

CAUDIO

I

CardBus audio. CAUDIO is a digital input signal from a PC Card to

 

 

the system speaker. The PCI4410A device supports the binary audio

 

 

mode and outputs a binary signal from the card to SPKROUT.

CBLOCK#

I/O

CardBus lock. CBLOCK# is used to gain exclusive access to a

 

 

target.

CCD1#

I

CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are

CCD2#

 

used in conjunction with CVS1 and CVS2 to identify card insertion

 

 

and interrogate cards to determine the operating voltage and card

 

 

type.

CDEVSEL#

I/O

CardBus device select. The PCI4410A device asserts CDEVSEL# to

 

 

claim a CardBus cycle as the target device. As a CardBus initiator on

 

 

the bus, the PCI4410A device monitors CDEVSEL# until a target

 

 

responds. If no target responds before timeout occurs, the PCI4410A

 

 

device terminates the cycle with an initiator abort.

CFRAME#

I/O

CardBus cycle frame. CFRAME# is driven by the initiator of a

 

 

CardBus bus cycle. CFRAME# is asserted to indicate that a bus

 

 

transaction is beginning, and data transfers continue while this signal

 

 

is asserted. When CFRAME# is deasserted, the CardBus bus

 

 

transaction is in the final data phase.

CGNT#

O

CardBus bus grant. CGNT# is driven by the PCI4410A device to

 

 

grant a CardBus PC Card access the CardBus bus after the current

 

 

data transaction has been completed.

CINT#

I

CardBus interrupt. CINT# is asserted low by a CardBus PC Card to

 

 

request interrupt servicing from the host.

CIRDY#

I/O

CardBus initiator ready. CIRDY indicates the CardBus initiator’s

 

 

ability to complete the current data

 

 

phase of the transaction. A data phase is completed on a rising edge

 

 

of CCLK when both CIRDY and

 

 

CTRDY are asserted. Until both CIRDY and CTRDY are sampled

 

 

asserted, wait states are inserted.

CPERR#

I/O

CardBus parity error. CPERR# reports parity errors during CardBus

 

 

transactions, except during special cycles. It is driven low by a target

 

 

two clocks following that data when a parity error is detected.

CREQ#

I

CardBus request. CREQ# indicates to the arbiter that the CardBus

 

 

PC Card desires use of the CardBus bus as an initiator.

CSERR#

I

CardBus system error. CSERR# reports address parity errors and

 

 

other system errors that could lead to catastrophic results. CSERR# is

 

 

driven by the card synchronous to CCLK, but deasserted by a weak

 

 

pull up, and may take several CCLK periods. The PCI4410A device

 

 

can report CSERR# to the system by assertion of SERR# on the PCI

 

 

interface.

Name

Type

Description

CSTOP#

I/O

CardBus stop. CSTOP# is driven by a CardBus target to request the

 

 

initiator to stop the current CardBus transaction. CSTOP# is used for

 

 

target disconnects, and is commonly asserted by target devices

 

 

do not support burst data transfers.

CSTSCHG#

I

CardBus status change. CSTSCHG alerts the system to a change in

 

 

the card’s status, and is used a wake-up mechanism.

CTRDY#

I/O

CardBus target ready. CTRDY# indicates the CardBus target’s

 

 

ability to complete the current data phase of the transaction. A data

 

 

phase is completed on a rising edge of CCLK, when both CIRDY and

 

 

CTRDY# are asserted; until this time, wait states are inserted.

CVS1

 

CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and

CVS2

 

CVS2 are used in conjunction with CCD1# and CCD2# to identify

 

 

card insertion and interrogate cards to determine the operating voltage

 

 

and card type.

IEEE 1394 PHY/Link Interface Terminals

Name

Type

Description

PHY_CTL1

I/O

PHY-link interface control. These bidirectional signals control

PHY_CTL0

 

passage of information between the PHY and link. The link can drive

 

 

these terminals only after the PHY has granted permission, following

 

 

a link request (LREQ).

PHY_DATA[0:7]

I/O

PHY-link interface data. These bidirectional signals pass data

 

 

between the PHY and link. These terminals are driven by the link on

 

 

transmissions and are driven by the PHY on receptions. Only

 

 

DATA1–DATA0 are valid for 100-Mbit speed. DATA4–DATA0 are

 

 

valid for 200-Mbit speed and DATA7–DATA0 are valid for 400-Mbit

 

 

speed.

PHY_CLK

I

System clock. This input provides a 49.152-MHz clock signal for

 

 

data synchronization.

PHY_REQ

O

Link request. This signal is driven by the link to initiate a request for

 

 

the PHY to perform some

 

 

service.

LINKON

I

1394 link on. This input from the PHY indicates that the link should

 

 

turn on.

LPS

O

Link power status. LPS indicates that link is powered and fully

 

 

functional.

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