8170 N/B MAINTENANCE
5.4 PCI4410(PCMCIA/1394 LINK Controller )
CardBus PC Card Interface Control Terminals
Name | Type | Description |
CAUDIO | I | CardBus audio. CAUDIO is a digital input signal from a PC Card to |
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| the system speaker. The PCI4410A device supports the binary audio |
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| mode and outputs a binary signal from the card to SPKROUT. |
CBLOCK# | I/O | CardBus lock. CBLOCK# is used to gain exclusive access to a |
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| target. |
CCD1# | I | CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are |
CCD2# |
| used in conjunction with CVS1 and CVS2 to identify card insertion |
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| and interrogate cards to determine the operating voltage and card |
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| type. |
CDEVSEL# | I/O | CardBus device select. The PCI4410A device asserts CDEVSEL# to |
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| claim a CardBus cycle as the target device. As a CardBus initiator on |
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| the bus, the PCI4410A device monitors CDEVSEL# until a target |
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| responds. If no target responds before timeout occurs, the PCI4410A |
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| device terminates the cycle with an initiator abort. |
CFRAME# | I/O | CardBus cycle frame. CFRAME# is driven by the initiator of a |
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| CardBus bus cycle. CFRAME# is asserted to indicate that a bus |
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| transaction is beginning, and data transfers continue while this signal |
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| is asserted. When CFRAME# is deasserted, the CardBus bus |
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| transaction is in the final data phase. |
CGNT# | O | CardBus bus grant. CGNT# is driven by the PCI4410A device to |
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| grant a CardBus PC Card access the CardBus bus after the current |
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| data transaction has been completed. |
CINT# | I | CardBus interrupt. CINT# is asserted low by a CardBus PC Card to |
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| request interrupt servicing from the host. |
CIRDY# | I/O | CardBus initiator ready. CIRDY indicates the CardBus initiator’s |
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| ability to complete the current data |
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| phase of the transaction. A data phase is completed on a rising edge |
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| of CCLK when both CIRDY and |
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| CTRDY are asserted. Until both CIRDY and CTRDY are sampled |
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| asserted, wait states are inserted. |
CPERR# | I/O | CardBus parity error. CPERR# reports parity errors during CardBus |
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| transactions, except during special cycles. It is driven low by a target |
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| two clocks following that data when a parity error is detected. |
CREQ# | I | CardBus request. CREQ# indicates to the arbiter that the CardBus |
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| PC Card desires use of the CardBus bus as an initiator. |
CSERR# | I | CardBus system error. CSERR# reports address parity errors and |
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| other system errors that could lead to catastrophic results. CSERR# is |
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| driven by the card synchronous to CCLK, but deasserted by a weak |
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| pull up, and may take several CCLK periods. The PCI4410A device |
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| can report CSERR# to the system by assertion of SERR# on the PCI |
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| interface. |
Name | Type | Description |
CSTOP# | I/O | CardBus stop. CSTOP# is driven by a CardBus target to request the |
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| initiator to stop the current CardBus transaction. CSTOP# is used for |
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| target disconnects, and is commonly asserted by target devices |
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| do not support burst data transfers. |
CSTSCHG# | I | CardBus status change. CSTSCHG alerts the system to a change in |
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| the card’s status, and is used a |
CTRDY# | I/O | CardBus target ready. CTRDY# indicates the CardBus target’s |
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| ability to complete the current data phase of the transaction. A data |
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| phase is completed on a rising edge of CCLK, when both CIRDY and |
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| CTRDY# are asserted; until this time, wait states are inserted. |
CVS1 |
| CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and |
CVS2 |
| CVS2 are used in conjunction with CCD1# and CCD2# to identify |
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| card insertion and interrogate cards to determine the operating voltage |
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| and card type. |
IEEE 1394 PHY/Link Interface Terminals
Name | Type | Description |
PHY_CTL1 | I/O | |
PHY_CTL0 |
| passage of information between the PHY and link. The link can drive |
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| these terminals only after the PHY has granted permission, following |
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| a link request (LREQ). |
PHY_DATA[0:7] | I/O | |
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| between the PHY and link. These terminals are driven by the link on |
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| transmissions and are driven by the PHY on receptions. Only |
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| |
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| valid for |
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| speed. |
PHY_CLK | I | System clock. This input provides a |
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| data synchronization. |
PHY_REQ | O | Link request. This signal is driven by the link to initiate a request for |
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| the PHY to perform some |
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| service. |
LINKON | I | 1394 link on. This input from the PHY indicates that the link should |
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| turn on. |
LPS | O | Link power status. LPS indicates that link is powered and fully |
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| functional. |
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