8170 N/B MAINTENANCE
5.4 PCI4410(PCMCIA/1394 LINK Controller )
PCI Interface Control Terminals
Name | Type | Description |
IRDY# | I/O | PCI initiator ready. IRDY# indicates the PCI bus initiator’s ability to |
|
| complete the current data phase of the transaction. A data phase is |
|
| completed on a rising edge of PCLK, when both IRDY# and TRDY# |
|
| are asserted. Until IRDY# and TRDY# are both sampled asserted, |
|
| wait states are inserted. |
PERR# | I/O | PCI parity error indicator. PERR# is driven by a PCI device to |
|
| indicate that calculated parity does not match PAR when PERR# is |
|
| enabled through bit 6 (PERR_EN) of the command register (PCI |
|
| offset 04h, see Section 4.4). |
REQ# | O | PCI bus request. REQ# is asserted by the PCI4410A device to request |
|
| access to the PCI bus as an initiator. |
SERR# | O | PCI system error. SERR# is an output that is pulsed from the |
|
| PCI4410A device when enabled through bit 8 (SERR_EN) of the |
|
| command register (PCI offset 04h, see Section 4.4) indicating a |
|
| system error has occurred. The PCI4410A device need not be the |
|
| target of the PCI cycle to assert this signal. When SERR# is enabled |
|
| in the command register, this signal also pulses, indicating that an |
|
| address parity error has occurred on a CardBus interface. |
STOP# | I/O | PCI cycle stop signal. STOP# is driven by a PCI target to request the |
|
| initiator to stop the current PCI bus transaction. STOP# is used for |
|
| target disconnects and is commonly asserted by target devices that do |
|
| not support burst data transfers. |
TRDY# | I/O | PCI target ready. TRDY# indicates the primary bus target’s ability to |
|
| complete the current data phase of the transaction. A data phase is |
|
| completed on a rising edge of PCLK, when both IRDY# and TRDY# |
|
| are asserted. Until both IRDY# and TRDY# are asserted, wait states |
|
| are inserted. |
Multifunction and Miscellaneous Terminals
Name | Type | Description |
INTA# | O | Parallel PCI interrupt. INTA# |
INTB# | O | Parallel PCI interrupt. INTB# |
LED_SKT | O | PC Card socket activity LED indicator. LED_SKT provides an output |
|
| indicating PC Card socket activity. |
MFUNC0 | I/O | Multifunction terminal 0. MFUNC0 can be configured as parallel PCI |
|
| interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV |
|
| switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. |
|
| See Section 4.32, Multifunction Routing Register, for configuration |
|
| details. |
Name | Type | Description |
MFUNC1 | I/O | Multifunction terminal 1. MFUNC1 can be configured as GPI1, |
|
| GPO1, socket activity LED output, ZV switching outputs, CardBus |
|
| audio PWM, GPE#, or a parallel IRQ. See Section 4.32, |
|
| Multifunction Routing Register, for configuration details. |
|
| Serial data (SDA). When VCCD0# and VCCD1# are high after a PCI |
|
| reset, the MFUNC1 terminal provides the SDA signaling for the serial |
|
| bus interface. The |
|
| identification and other register defaults from an EEPROM after a |
|
| PCI reset. See Section 3.6.1, Serial Bus Interface Implementation, for |
|
| details on other serial bus applications. |
MFUNC2 | I/O | Multifunction terminal 2. MFUNC2 can be configured as PC/PCI |
|
| DMA request, GPI2, GPO2, ZV switching outputs, CardBus audio |
|
| PWM, GPE#, RI_OUT#, or a parallel IRQ. See Section 4.32, |
|
| Multifunction Routing Register, for configuration details. |
MFUNC3 | I/O | Multifunction terminal 3. MFUNC3 can be configured as a parallel |
|
| IRQ or the serialized interrupt signal IRQSER. See Section 4.32, |
|
| Multifunction Routing Register, for configuration details. |
MFUNC4 | I/O | Multifunction terminal 4. MFUNC4 can be configured as PCI |
|
| LOCK#, GPI3, GPO3, socket activity LED output, ZV switching |
|
| outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. |
|
| See Section 4.32, Multifunction Routing Register, for configuration |
|
| details. Serial clock (SCL). When VCCD0# and VCCD1# are high |
|
| after a PCI reset, the MFUNC4 terminal provides the SCL signaling |
|
| for the serial bus interface. The |
|
| subsystem identification and other register defaults from an EEPROM |
|
| after a PCI reset. See Section 3.6.1, Serial Bus Interface |
|
| Implementation, for details on other serial bus applications. |
MFUNC5 | I/O | Multifunction terminal 5. MFUNC5 can be configured as PC/PCI |
|
| DMA grant, GPI4, GPO4, socket activity LED output, ZV switching |
|
| outputs, CardBus audio PWM, GPE#, or a parallel IRQ. See Section |
|
| 4.32, Multifunction Routing Register, for configuration details. |
MFUNC6 | I/O | Multifunction terminal 6. MFUNC6 can be configured as a PCI |
|
| CLKRUN# or a parallel IRQ. See Section 4.32, Multifunction |
|
| Routing Register, for configuration details. |
RI_OUT#/PME# | O | Ring indicate out and |
|
| provides an output for |
SPKROUT | O | Speaker output. SPKROUT is the output to the host system that can |
|
| carry SPKR# or CAUDIO through the PCI4410A device from the PC |
|
| Card interface. SPKROUT is driven as the |
|
| of card SPKR#//CAUDIO inputs. |
SUSPEND# | I | Suspend. SUSPEND# protects the internal registers from clearing |
|
| when the GRST or PRST signal is asserted. See Section 3.8.4, |
|
| Suspend Mode, for details. |
131