8170 N/B MAINTENANCE
5.1 Pentium 4(Willamette/Northwood)
Name | Type | Description |
LINT[1:0] | Input | LINT[1:0] (Local APIC Interrupt) must connect the appropriate |
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| pins of all APIC Bus agents. When the APIC is disabled, the |
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| LINT0 signal becomes INTR, a maskable interrupt request |
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| signal, and LINT1 becomes NMI, a nonmaskable interrupt. |
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| INTR and NMI are backward compatible with the signals of |
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| those names on the Pentium processor. Both signals are |
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| asynchronous. |
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| Both of these signals must be software configured via BIOS |
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| programming of the APIC register space to be used either as |
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| NMI/INTR or LINT[1:0]. Because the APIC is enabled by |
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| default after Reset, operation of these pins as LINT[1:0] is the |
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| default configuration. |
LOCK# | Input/ | LOCK# indicates to the system that a transaction must occur |
| Output | atomically. This signal must connect the appropriate pins of all |
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| processor system bus agents. For a locked sequence of |
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| transactions, LOCK# is asserted from the beginning of the |
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| first transaction to the end of the last transaction. |
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| When the priority agent asserts BPRI# to arbitrate for ownership |
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| of the processor system bus, it will wait until it observes |
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| LOCK# deasserted. This enables symmetric agents to retain |
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| ownership of the processor system bus throughout the bus |
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| locked operation and ensure the atomicity of lock. |
MCERR# | Input/ | MCERR# (Machine Check Error) is asserted to indicate an |
| Output | unrecoverable error without a bus protocol violation. It may be |
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| driven by all processor system bus agents. |
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| MCERR# assertion conditions are configurable at a system |
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| level. Assertion options are defined by the following options: |
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| Enabled or disabled. |
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| Asserted, if configured, for internal errors along with IERR#. |
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| Asserted, if configured, by the request initiator of a bus |
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| transaction after it observes an error. |
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| Asserted by any bus agent when it observes an error in a bus |
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| transaction. |
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| For more details regarding machine check architecture, please |
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| refer to the |
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| System Programming Guide. |
PROCHOT# | Output | PROCHOT# will go active when the processor temperature |
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| monitoring sensor detects that the processor has reached its |
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| maximum safe operating temperature. |
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| This indicates that the processor Thermal Control Circuit has |
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| been activated, if enabled. |
Name | Type | Description |
PWRGOOD | Input | PWRGOOD (Power Good) is a processor input. The processor |
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| requires this signal to be a clean indication that the clocks and |
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| power supplies are stable and within their specifications. |
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| ‘Clean’ implies that the signal will remain low (capable of |
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| sinking leakage current), without glitches, from the time that the |
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| power supplies are turned on until they come within |
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| specification. The signal must then transition monotonically to a |
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| high illustrates the relationship of PWRGOOD to the RESET# |
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| signal. PWRGOOD can be driven inactive at any time, but |
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| clocks and power must again be stable before a subsequent |
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| rising edge of PWRGOOD. It must also meet the minimum |
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| pulse width and be followed by a 1 to 10 ms RESET# pulse. |
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| The PWRGOOD signal must be supplied to the processor; it is |
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| used to protect internal circuits against voltage sequencing |
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| issues. It should be driven high |
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| throughout boundary scan operation. |
RESET# | Input | Asserting the RESET# signal resets the processor to a known |
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| state and invalidates its internal caches without writing back any |
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| of their contents. For a |
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| active for at least one millisecond after VCC and BCLK have |
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| reached their proper specifications. On observing active |
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| RESET#, all system bus agents will deassert their outputs within |
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| two clocks. RESET# must not be kept asserted for more than 10 |
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| ms while PWRGOOD is asserted. |
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| A number of bus signals are sampled at the |
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| transition of RESET# for |
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| This signal does not have |
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| terminated on the system board. |
RS[2:0]# | Input | RS[2:0]# (Response Status) are driven by the response agent |
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| (the agent responsible for completion of the current transaction), |
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| and must connect the appropriate pins of all processor system |
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| bus agents. |
RSP# | Input | RSP# (Response Parity) is driven by the response agent (the |
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| agent responsible for completion of the current transaction) |
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| during assertion of RS[2:0]#, the signals for which RSP# |
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| provides parity protection. It must connect to the appropriate |
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| pins of all processor system bus agents. |
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| A correct parity signal is high if an even number of covered |
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| signals are low and low if an odd number of covered signals are |
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| low. While RS[2:0]# = 000, RSP# is also high, since this |
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| indicates it is not being driven by any agent guaranteeing |
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| correct parity. |
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