8170 N/B MAINTENANCE

5.1 Pentium 4(Willamette/Northwood) mFC-PGA2 478 pin

Name

Type

Description

LINT[1:0]

Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate

 

 

pins of all APIC Bus agents. When the APIC is disabled, the

 

 

LINT0 signal becomes INTR, a maskable interrupt request

 

 

signal, and LINT1 becomes NMI, a nonmaskable interrupt.

 

 

INTR and NMI are backward compatible with the signals of

 

 

those names on the Pentium processor. Both signals are

 

 

asynchronous.

 

 

Both of these signals must be software configured via BIOS

 

 

programming of the APIC register space to be used either as

 

 

NMI/INTR or LINT[1:0]. Because the APIC is enabled by

 

 

default after Reset, operation of these pins as LINT[1:0] is the

 

 

default configuration.

LOCK#

Input/

LOCK# indicates to the system that a transaction must occur

 

Output

atomically. This signal must connect the appropriate pins of all

 

 

processor system bus agents. For a locked sequence of

 

 

transactions, LOCK# is asserted from the beginning of the

 

 

first transaction to the end of the last transaction.

 

 

When the priority agent asserts BPRI# to arbitrate for ownership

 

 

of the processor system bus, it will wait until it observes

 

 

LOCK# deasserted. This enables symmetric agents to retain

 

 

ownership of the processor system bus throughout the bus

 

 

locked operation and ensure the atomicity of lock.

MCERR#

Input/

MCERR# (Machine Check Error) is asserted to indicate an

 

Output

unrecoverable error without a bus protocol violation. It may be

 

 

driven by all processor system bus agents.

 

 

MCERR# assertion conditions are configurable at a system

 

 

level. Assertion options are defined by the following options:

 

 

Enabled or disabled.

 

 

Asserted, if configured, for internal errors along with IERR#.

 

 

Asserted, if configured, by the request initiator of a bus

 

 

transaction after it observes an error.

 

 

Asserted by any bus agent when it observes an error in a bus

 

 

transaction.

 

 

For more details regarding machine check architecture, please

 

 

refer to the IA-32 Software Developer’s Manual, Volume 3:

 

 

System Programming Guide.

PROCHOT#

Output

PROCHOT# will go active when the processor temperature

 

 

monitoring sensor detects that the processor has reached its

 

 

maximum safe operating temperature.

 

 

This indicates that the processor Thermal Control Circuit has

 

 

been activated, if enabled.

Name

Type

Description

PWRGOOD

Input

PWRGOOD (Power Good) is a processor input. The processor

 

 

requires this signal to be a clean indication that the clocks and

 

 

power supplies are stable and within their specifications.

 

 

‘Clean’ implies that the signal will remain low (capable of

 

 

sinking leakage current), without glitches, from the time that the

 

 

power supplies are turned on until they come within

 

 

specification. The signal must then transition monotonically to a

 

 

high illustrates the relationship of PWRGOOD to the RESET#

 

 

signal. PWRGOOD can be driven inactive at any time, but

 

 

clocks and power must again be stable before a subsequent

 

 

rising edge of PWRGOOD. It must also meet the minimum

 

 

pulse width and be followed by a 1 to 10 ms RESET# pulse.

 

 

The PWRGOOD signal must be supplied to the processor; it is

 

 

used to protect internal circuits against voltage sequencing

 

 

issues. It should be driven high

 

 

throughout boundary scan operation.

RESET#

Input

Asserting the RESET# signal resets the processor to a known

 

 

state and invalidates its internal caches without writing back any

 

 

of their contents. For a power-on Reset, RESET# must stay

 

 

active for at least one millisecond after VCC and BCLK have

 

 

reached their proper specifications. On observing active

 

 

RESET#, all system bus agents will deassert their outputs within

 

 

two clocks. RESET# must not be kept asserted for more than 10

 

 

ms while PWRGOOD is asserted.

 

 

A number of bus signals are sampled at the active-to-inactive

 

 

transition of RESET# for power-on configuration.

 

 

This signal does not have on-die termination and must be

 

 

terminated on the system board.

RS[2:0]#

Input

RS[2:0]# (Response Status) are driven by the response agent

 

 

(the agent responsible for completion of the current transaction),

 

 

and must connect the appropriate pins of all processor system

 

 

bus agents.

RSP#

Input

RSP# (Response Parity) is driven by the response agent (the

 

 

agent responsible for completion of the current transaction)

 

 

during assertion of RS[2:0]#, the signals for which RSP#

 

 

provides parity protection. It must connect to the appropriate

 

 

pins of all processor system bus agents.

 

 

A correct parity signal is high if an even number of covered

 

 

signals are low and low if an odd number of covered signals are

 

 

low. While RS[2:0]# = 000, RSP# is also high, since this

 

 

indicates it is not being driven by any agent guaranteeing

 

 

correct parity.

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