8170 N/B MAINTENANCE

5.2 Intel 82845(Brookdale Memory Controller HUB)

AGP Strobes Signals

Name

Type

Description

AD_STB0

I/O

Address/Data Bus Strobe-0:This signal provides timing for 2x and

 

(s/t/s)

4x data on AD[15:0] and the C/BE[1:0]# signals. The agent that is

 

AGP

providing the data drives this signal.

 

 

 

AD_STB0#

I/O

Address/Data Bus Strobe-0 Compliment: Differential strobe pair

 

(s/t/s)

that provides timing information for the AD[15:0] and C/BE[1:0]#

 

AGP

signals. The agent that is providing the data drives this signal.

 

 

 

AD_STB1

I/O

Address/Data Bus Strobe-1:This signal provides timing for 2x- and

 

(s/t/s)

4x-clocked data on AD[31:16] and C/BE[3:2]# signals. The agent that

 

AGP

is providing the data drives this signal.

AD_STB1#

I/O

Address/Data Bus Strobe-1 Compliment: The differential

 

(s/t/s)

compliment to the AD_STB1 signal. It is used to provide timing for

 

AGP

4x-clocked data.

SB_STB

I

Sideband Strobe: This signal provides timing for 2x- and 4x-

 

AGP

clocked data on the SBA[7:0] bus. It is driven by the AGP master

 

 

after the system has been configured for 2x- or 4x- clocked sideband

 

 

address delivery.

SB_STB#

I

Sideband Strobe Compliment: SB_STB# is the differential

 

AGP

compliment to the SB_STB signal. It is used to provide timing for

 

 

4x-clocked data.

AGP/PCISignals

For transactions on the AGP interface carried using AGP FRAME# protocol, these signals operate similar to their semantics in the PCI 2.1 specification the exact role of all AGP FRAME# signals are defined below.

Name

Type

Description

G_FRAME#

I/O

FRAME: During FRAME# Operations, G_FRAME# is an output

 

(s/t/s)

when the MCH acts as an initiator on the AGP Interface.

 

AGP

 

 

 

 

G_IRDY#

I/O

Initiator Ready#: This signal indicates the AGP compliant master is

 

(s/t/s)

ready to provide all write data for the current transaction. Once

 

AGP

G_IRDY# is asserted for a write operation, the master is not allowed

 

 

to insert wait states. The master is never allowed to insert a wait state

 

 

during the initial data transfer (32 bytes) of a write transaction.

 

 

However, it may insert wait states after each 32-byte block is

 

 

transferred.

Name

Type

Description

G_TRDY#

I/O

Target Ready: This signal indicates the AGP compliant target is

 

(s/t/s)

ready to provide read data for the entire transaction (when the transfer

 

AGP

size is less than or equal to 32 bytes) or is ready to transfer the initial

 

 

or subsequent block (32 bytes) of data when the transfer size is

 

 

greater than 32 bytes. The target is allowed to insert wait states after

 

 

each block (32 bytes) is transferred on write transactions.

G_STOP#

I/O

STOP: G_STOP Is an input when the MCH acts as a FRAME#-based

 

(s/t/s)

AGP initiator and an output when the MCH acts as a FRAME#-based

 

AGP

AGP target. G_STOP# is used for disconnect, retry, and abort

 

 

sequences on the AGP interface.

G_DEVSEL#

I/O

Device Select: This signal indicates that a FRAME#-based AGP

 

(s/t/s)

target device has decoded its address as the target of the current

 

AGP

access. The MCH asserts G_DEVSEL# based on the DRAM address

 

 

range being accessed by a PCI initiator. As an input it indicates

 

 

whether any device on the bus has been selected.

G_REQ#

I

Request: Indicates that a FRAME# or PIPE#-based AGP master is

 

AGP

requesting use of the AGP interface. This signal is an input into the

 

 

MCH.

G_GNT#

O

Grant: During SBA, PIPE# and FRAME# operation, G_GNT#,

 

AGP

along with the information on the ST[2:0] signals (status bus),

 

 

indicates how the AGP interface will be used next.

G_AD[31:0]

I/O

Address/Data Bus: These signals are used to transfer both address

 

AGP

and data on the AGP interface.

G_C/BE[3:0]#

I/O

Command/Byte Enable:

 

AGP

During FRAME# Operation: During the address phase of a

 

 

transaction, G_C/BE[3:0]# define the bus command. During the data

 

 

phase, G_C/BE[3:0]# are used as byte enables. The byte enables

 

 

determine which byte lanes carry meaningful data.

 

 

During PIPE# Operation: When an address is enqueued using

 

 

PIPE#, the G_C/BE# signals carry command information. The

 

 

command encoding used during PIPE#-based AGP is DIFFERENT

 

 

than the command encoding used during FRAME#-based AGP cycles

 

 

(or standard PCI cycles on a PCI bus).

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