8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
System Management Interface Signals
Name | Type | Description |
INTRUDER# | I | Intruder Detect: This signal can be set to disable system if box |
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| detected open. This signal’s status is readable, so it can be used like a |
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| GPI if the Intruder Detection is not needed. |
SMLINK[1:0] | I/OD | System Management Link: These signals are an SMBus link to an |
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| optional external system management ASIC or LAN controller. |
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| External |
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| Note: |
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| that SMLINK[0] corresponds to an SMBus Clock signal and |
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| SMLINK[1] corresponds to an SMBus Data signal. |
Real Time Clock Interface
Name | Type | Description |
RTCX1 | Special | Crystal Input 1: This signal is connected to the 32.768 KHz crystal. |
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| If no external crystal is used, then RTCX1 can be driven with the |
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| desired clock rate. |
RTCX2 | Special | Crystal Input 2: This signal is connected to the 32.768 KHz crystal. |
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| If no external crystal is used, then RTCX2 should be left floating. |
Other Clocks
Name | Type | Description |
CLK14 | I | Oscillator Clock: CLK14 is used for 8254 timers and runs at |
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| 14.31818 MHz. |
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| 82801BA ICH2: This clock is permitted to stop during S3 (or lower) |
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| states. |
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| 82801BAM |
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| lower) states. |
CLK48 | I | 48 MHz Clock: CLK48 is used to for the USB controller and runs at |
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| 48 MHz. |
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| 82801BA ICH2: This clock is permitted to stop during S3 (or lower) |
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| states. |
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| 82801BAM |
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| lower) states. |
CLK66 | I | 66 MHz Clock: CLK66 is used to for the hub interface and runs at 66 |
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| MHz. |
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| 82801BA ICH2: This clock is permitted to stop during S3 (or lower) |
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| states. |
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| 82801BAM |
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| lower) states. |
Miscellaneous Signals
Name | Type | Description |
SPKR | O | Speaker: The SPKR signal is the output of counter 2 and is internally |
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| "ANDed" with Port 61h bit 1 to provide Speaker Data Enable. This |
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| signal drives an external speaker driver device, which in turn drives |
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| the system speaker. Upon PCIRST#, its output state is 1. |
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| Note: |
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| SPKR is sampled at the rising edge of PWROK as a functional strap. |
RTCRST# | I | RTC Reset: When asserted, this signal resets register bits in the RTC |
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| well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 |
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| register). Note: |
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| Clearing CMOS in an |
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| jumper on RTCRST# or GPI, or using SAFEMODE strap. |
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| Implementations should not attempt to clear CMOS by using a |
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| jumper to pull VccRTC low. |
TP0 | I | Test Point (82801BA ICH2): This signal must have an external |
(ICH2 0nly) |
| |
FS0 | I | Functional Strap: This signal is reserved for future use. There is an |
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| internal pullup resistor on this signal. |
AC’97 Link Signals
Name | Type | Description |
AC_RST# | O | AC97 Reset: Master H/W reset to external Codec(s) |
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AC_SYNC | O | AC97 Sync: 48 KHz fixed rate sample sync to the Codec(s) |
AC_BIT_CLK | I | AC97 Bit Clock: 12.288 MHz serial data clock generated by the |
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| external Codec(s). See Note. |
AC_SDOUT | O | AC97 Serial Data Out: Serial TDM data output to the Codec(s) |
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| Note: |
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| AC_SDOUT is sampled at the rising edge of PWROK as a functional |
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| strap.. |
AC_SDIN[1:0] | I | AC97 Serial Data In 0: Serial TDM data inputs from the Codecs. |
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| See Note. |
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