8170 N/B MAINTENANCE

5.4 PCI4410(PCMCIA/1394 LINK Controller )

Power-Supply Terminals

Name

Type

Description

GND

 

Device ground terminals

 

 

 

VCC

 

Power-supply terminal for core logic (3.3 V)

VCCB

 

Clamp voltage for PC Card interface. Matches card signaling

 

 

environment, 5 V or 3.3 V.

VCCI

 

Clamp voltage for miscellaneous I/O signals (MFUNC, GRST#, and

 

 

SUSPEND#)

VCCL

 

Clamp voltage for 1394 link function

 

 

 

VCCP

 

Clamp voltage for PCI interface, ZV interface, SPKROUT, INTA#,

 

 

INTB# LED_SKT,VCCD0#, VCCD1#, VPPD0, VPPD1

PC Card Power-Switch Terminals

Name

Type

 

Description

VCCD0#

O

Logic controls to the TPS2211 PC Card power-switch interface to

VCCD1#

 

control AVCC

 

VPPD0

O

Logic controls to the TPS2211 PC Card power-switch interface to

VPPD1

 

control AVPP

 

PCI System Terminals

Name

Type

Description

GRST#

I

Global reset. When global reset is asserted, GRST# causes the

 

 

PCI4410A device to place all output buffers in a high-impedance

 

 

state and reset all internal registers. When GRST# is asserted, the

 

 

device is completely in its default state. For systems that require

 

 

wake-up from D3, GRST# normally is asserted only during initial

 

 

boot. PRST# should be asserted following initial boot so that PME

 

 

context is retained when transitioning from D3 to D0. For systems

 

 

that do not require wake-up from D3, GRST# should be tied to PRST.

 

 

When the SUSPEND mode is enabled, the device is protected from

 

 

GRST#, and the internal registers are preserved. All outputs are

 

 

placed in a high-impedance state, but the contents of the registers are

 

 

preserved.

PCLK

I

PCI bus clock. PCLK provides timing for all transactions on the PCI

 

 

bus. All PCI signals are sampled at the rising edge of PCLK.

PRST#

I

PCI bus reset. When the PCI bus reset is asserted, PRST# causes the

 

 

PCI4410A device to place all output buffers in a high-impedance

 

 

state and reset internal registers. When PRST is asserted, the device is

 

 

completely nonfunctional. After PRST# is deserted, the PCI4410A

 

 

device is in a default state. When SUSPEND# and PRST# are

 

 

asserted, the device is protected from PRST# clearing the internal

 

 

registers.All outputs are placed in a high-impedance state, but the

 

 

contents of the registers are preserved.

PCI Address and Data Terminals

Name

Type

Description

AD[0:31[

I/O

PCI address/data bus. These signals make up the multiplexed PCI

 

 

address and data bus on the primary interface. During the address

 

 

phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit

 

 

address or other destination information. During the data phase,

 

 

AD31–AD0 contain data.

C/BE[0:3]#

I/O

PCI bus commands and byte enables. These signals are multiplexed

 

 

on the same PCI terminals. During the address phase of a primary bus

 

 

PCI cycle, C/BE3#–C/BE0# define the bus command. During the data

 

 

phase, this 4-bit bus is used as byte enables. The byte enables

 

 

determine which byte paths of the full 32-bit data bus carry

 

 

meaningful data. C/BE0# applies to byte 0 (AD7–AD0), C/BE1#

 

 

applies to byte 1 (AD15–AD8), C/BE2# applies to byte 2

 

 

(AD23–AD16), and C/BE3# applies to byte 3 (AD31–AD24).

PAR

I/O

PCI bus parity. In all PCI bus read and write cycles, the PCI4410A

 

 

device calculates even parity across the AD31–AD0 and

 

 

C/BE3#–C/BE0# buses. As an initiator during PCI cycles, the

 

 

PCI4410A device outputs this parity indicator with a one-PCLK

 

 

delay. As a target during PCI cycles, the calculated parity is compared

 

 

to the initiator’s parity indicator. A compare error results in the

 

 

assertion of a parity error (PERR#).

PCI Interface Control Terminals

Name

Type

Description

DECSEL#

I/O

PCI device select. The PCI4410A device asserts DEVSEL# to claim a

 

 

PCI cycle as the target device. As a PCI initiator on the bus, the

 

 

PCI4410A device monitors DEVSEL# until a target responds. If no

 

 

target responds before timeout occurs, the PCI4410A device

 

 

terminates the cycle with an initiator abort.

FRAME#

I/O

PCI cycle frame. FRAME# is driven by the initiator of a bus cycle.

 

 

FRAME# is asserted to indicate that a bus transaction is beginning,

 

 

and data transfers continue while this signal is asserted. When

 

 

FRAME# is deasserted, the PCI bus transaction is in the final data

 

 

phase.

GNT#

I

PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the

 

 

PCI4410A device access to the PCI bus after the current data

 

 

transaction has completed. GNT# may or may not follow a PCI bus

 

 

request, depending on the PCI bus parking algorithm.

IDSEL#

I

Initialization device select. IDSEL# selects the PCI4410A device

 

 

during configuration space accesses. IDSEL# can be connected to one

 

 

of the upper 24 PCI address lines on the PCI bus.

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