8170 N/B MAINTENANCE
5.4 PCI4410(PCMCIA/1394 LINK Controller )
Name | Type | Description |
GND |
| Device ground terminals |
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VCC |
| |
VCCB |
| Clamp voltage for PC Card interface. Matches card signaling |
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| environment, 5 V or 3.3 V. |
VCCI |
| Clamp voltage for miscellaneous I/O signals (MFUNC, GRST#, and |
|
| SUSPEND#) |
VCCL |
| Clamp voltage for 1394 link function |
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VCCP |
| Clamp voltage for PCI interface, ZV interface, SPKROUT, INTA#, |
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| INTB# LED_SKT,VCCD0#, VCCD1#, VPPD0, VPPD1 |
PC Card
Name | Type |
| Description |
VCCD0# | O | Logic controls to the TPS2211 PC Card | |
VCCD1# |
| control AVCC |
|
VPPD0 | O | Logic controls to the TPS2211 PC Card | |
VPPD1 |
| control AVPP |
|
PCI System Terminals
Name | Type | Description |
GRST# | I | Global reset. When global reset is asserted, GRST# causes the |
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| PCI4410A device to place all output buffers in a |
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| state and reset all internal registers. When GRST# is asserted, the |
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| device is completely in its default state. For systems that require |
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| |
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| boot. PRST# should be asserted following initial boot so that PME |
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| context is retained when transitioning from D3 to D0. For systems |
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| that do not require |
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| When the SUSPEND mode is enabled, the device is protected from |
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| GRST#, and the internal registers are preserved. All outputs are |
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| placed in a |
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| preserved. |
PCLK | I | PCI bus clock. PCLK provides timing for all transactions on the PCI |
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| bus. All PCI signals are sampled at the rising edge of PCLK. |
PRST# | I | PCI bus reset. When the PCI bus reset is asserted, PRST# causes the |
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| PCI4410A device to place all output buffers in a |
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| state and reset internal registers. When PRST is asserted, the device is |
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| completely nonfunctional. After PRST# is deserted, the PCI4410A |
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| device is in a default state. When SUSPEND# and PRST# are |
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| asserted, the device is protected from PRST# clearing the internal |
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| registers.All outputs are placed in a |
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| contents of the registers are preserved. |
PCI Address and Data Terminals
Name | Type | Description |
AD[0:31[ | I/O | PCI address/data bus. These signals make up the multiplexed PCI |
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| address and data bus on the primary interface. During the address |
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| phase of a primary bus PCI cycle, |
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| address or other destination information. During the data phase, |
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| |
C/BE[0:3]# | I/O | PCI bus commands and byte enables. These signals are multiplexed |
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| on the same PCI terminals. During the address phase of a primary bus |
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| PCI cycle, |
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| phase, this |
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| determine which byte paths of the full |
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| meaningful data. C/BE0# applies to byte 0 |
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| applies to byte 1 |
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| |
PAR | I/O | PCI bus parity. In all PCI bus read and write cycles, the PCI4410A |
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| device calculates even parity across the |
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| |
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| PCI4410A device outputs this parity indicator with a |
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| delay. As a target during PCI cycles, the calculated parity is compared |
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| to the initiator’s parity indicator. A compare error results in the |
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| assertion of a parity error (PERR#). |
PCI Interface Control Terminals
Name | Type | Description |
DECSEL# | I/O | PCI device select. The PCI4410A device asserts DEVSEL# to claim a |
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| PCI cycle as the target device. As a PCI initiator on the bus, the |
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| PCI4410A device monitors DEVSEL# until a target responds. If no |
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| target responds before timeout occurs, the PCI4410A device |
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| terminates the cycle with an initiator abort. |
FRAME# | I/O | PCI cycle frame. FRAME# is driven by the initiator of a bus cycle. |
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| FRAME# is asserted to indicate that a bus transaction is beginning, |
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| and data transfers continue while this signal is asserted. When |
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| FRAME# is deasserted, the PCI bus transaction is in the final data |
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| phase. |
GNT# | I | PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the |
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| PCI4410A device access to the PCI bus after the current data |
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| transaction has completed. GNT# may or may not follow a PCI bus |
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| request, depending on the PCI bus parking algorithm. |
IDSEL# | I | Initialization device select. IDSEL# selects the PCI4410A device |
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| during configuration space accesses. IDSEL# can be connected to one |
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| of the upper 24 PCI address lines on the PCI bus. |
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