8170 N/B MAINTENANCE
5.3 Intel 82801BA(I/O Controller HUB )
Processor Interface Signals
Name | Type | Description |
A20M# | O | Mask A20: A20M# goes active based on setting the appropriate bit in |
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| the Port 92h register, or based on the A20GATE signal. |
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| Speed Strap: During the reset sequence, ICH2 drives A20M# high if |
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| the corresponding bit is set in the FREQ_STRP register. |
CPUSLP# | O | Processor Sleep: This signal puts the processor into a state that saves |
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| substantial power compared to |
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| time, no snoops occur. The ICH2 can optionally assert the CPUSLP# |
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| signal when going to the S1 state. |
FERR# | I | Numeric Coprocessor Error: This signal is tied to the coprocessor |
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| error signal on the processor. FERR# is only used if the ICH2 |
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| coprocessor error reporting function is enabled in the General Control |
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| Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is |
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| asserted, the ICH2 generates an internal IRQ13 to its interrupt |
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| controller unit. It is also used to gate the IGNNE# signal to ensure |
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| that IGNNE# is not asserted to the processor unless FERR# is active. |
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| FERR# requires an external weak |
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| the coprocessor error function is disabled. |
IGNNE# | O | Ignore Numeric Error: This signal is connected to the ignore error |
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| pin on the processor. IGNNE# is only used if the ICH2 coprocessor |
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| error reporting function is enabled in the General Control Register |
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| (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, |
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| indicating a coprocessor error, a write to the Coprocessor Error |
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| Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains |
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| asserted until FERR# is negated. If FERR# is not asserted when the |
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| Coprocessor Error Register is written, the IGNNE# signal is not |
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| asserted. |
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| Speed Strap: During the reset sequence, ICH2 drives IGNNE# high |
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| if the corresponding bit is set in the FREQ_STRP register. |
INIT# | O | Initialization: INIT# is asserted by the ICH2 for 16 PCI clocks to |
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| reset the processor. ICH2 can be configured to support processor |
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| BIST. In that case, INIT# will be active when PCIRST# is active. |
INTR | O | Processor Interrupt: INTR is asserted by the ICH2 to signal the |
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| processor that an interrupt request is pending and needs to be |
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| serviced. It is an asynchronous output and normally driven low. |
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| Speed Strap: During the reset sequence, ICH2 drives INTR high if |
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| the corresponding bit is set in the FREQ_STRP register. |
NMI | O | |
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| interrupt to the processor. The ICH2 can generate an NMI when |
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| either SERR# or IOCHK# is asserted. The processor detects an NMI |
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| when it detects a rising edge on NMI. NMI is reset by setting the |
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| corresponding NMI source enable/disable bit in the NMI Status and |
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| Control Register. |
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| Speed Strap: During the reset sequence, ICH2 drives NMI high if the |
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| corresponding bit is set in the FREQ_STRP register. |
Name | Type | Description |
SMI# | O | System Management Interrupt: SMI# is an active low output |
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| synchronous to PCICLK. It is asserted by the ICH2 in response to one |
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| of many enabled hardware or software events. |
STPCLK# | O | Stop Clock Request: STPCLK# is an active low output synchronous |
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| to PCICLK. It is asserted by the ICH2 in response to one of many |
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| hardware or software events. When the processor samples STPCLK# |
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| asserted, it responds by stopping its internal clock. |
RCIN# | I | Keyboard Controller Reset Processor: The keyboard controller can |
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| generate INIT# to the processor. This saves the external OR gate with |
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| the ICH2’s other sources of INIT#. When the ICH2 detects the |
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| assertion of this signal, INIT# isgenerated for 16 PCI clocks.. |
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| Note: |
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| 82801BA ICH2: The 82801BA ignores RCIN# assertion during |
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| transitions to the S3, S4 and S5 states. 82801BAM |
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| 82801BAM ignores RCIN# assertion during transitions |
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| to the S1, S3, S4 and S5 states. |
A20GATE | I | A20 Gate: This signal is from the keyboard controller. It acts as an |
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| alternative method to force the A20M# signal active. A20GATE |
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| saves the external OR gate needed with various other PCIsets. |
CPUPWRGD | OD | CPU Power Good (82801BAM |
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| connected to the processor’s PWRGOOD input. For Intel® |
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| SpeedStep™ technology support, this signal is kept high during a |
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| Intel® SpeedStep™ technology state transition to prevent loss of |
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| processor context. This is an |
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SM Bus Interface Signals
Name | Type | Description |
SMBDATA | I/OD | SMBus Data: External |
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SMBCLK | I/OD | SMBus Clock: External |
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SMBALERT#/ | I | SMBus Alert: This signal is used to wake the system or generate an |
GPIO[11] |
| SMI#. If not used for SMBALERT#, it can be used as a GPI. |
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