8170 N/B MAINTENANCE
External Glue Integration
---Integrated Pull-up, Pull-down and Series Termination resistors on IDE and processor interface Enhanced Hub I/F buffers improve routing flexibility (Not available with all Memory Controller Hubs)
Firmware Hub (FWH) I/F supports BIOS memory size up to 8 MBs
Low Pin count (LPC) I/F
---Allows connection of legacy ISA and X-Bus devices such as Super I/O
---Supports two Master/DMA devices.
Enhanced DMA Controller
---Two cascaded 8237 DMA controllers
---PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs
---Supports LPC DMA
---Supports DMA Collection Buffer to provide Type-F DMA performance for all DMA channels
Real-Time Clock
---256-byte battery-backed CMOS RAM
---Hardware implementation to indicate century rollover
System TCO Reduction Circuits
---Timers to generate SMI# and Reset upon detection of system hang
---Timers to detect improper processor reset
---Integrated processor frequency strap logic
SM Bus
---Host interface allows processor to communicate via SM Bus
---Slave interface allows an external Micro controller to access system resources
---Compatible with most 2-Wire components that are also I2C compatible