Introduction, General Description | Motorola MVME197LE manual

GENERAL INFORMATION

1

Introduction

This user’s manual provides general information, preparation for use and installation instructions, operating instructions, and a functional description for the MVME197LE version of the MVME197 series of single board computers.

General Description

The MVME197LE module is a double-high VMEmodule based on the MC88110 RISC microprocessor. The MVME197LE has 32/64MB of DRAM, 1MB of FLASH memory, 8KB of static RAM (with battery backup), a time of day clock (with battery backup), an Ethernet transceiver interface, four serial ports with EIA-232-D interface, six tick timers, a watchdog timer, 128/256KB of BOOT ROM, a SCSI bus interface with DMA (Direct Memory Access), a Centronics printer port, an A16/A24/A32/D8/D16/D32 VMEbus master/slave interface, and a VMEbus system controller.

Input/Output (I/O) signals are routed through the MVME197LE’s backplane connector P2. A P2 Adapter Board or LCP2 Adapter board routes the signals and grounds from connector P2 to an MVME712 series transition module. The MVME197LE supports the MVME712M, MVME712A, MVME712AM, and MVME712B transition boards (referred to here as the MVME712X, unless separately specified). The MVME197LE also supports the MVME712-12 and MVME712-13 (referred to as the MVME712-XX, unless separately specified). These transition boards provide configuration headers, serial port drivers, and industry standard connectors for the I/O devices.

The MVME197LE modules have eight ASICs (Application-Specific Integrated Circuits) described in the following order: BusSwitch, DCAM, ECDM, PCC2, and VME2.

The BusSwitch ASIC provides an interface between the processor bus (MC88110 bus) and the local peripheral bus (MC68040 compatible bus). Refer to the MVME197LE block diagram (Figure 1-1). It provides bus arbitration for the MC88110 bus and serves as a seven level interrupt handler. It has programmable map decoders for both busses, as well as write post buffers on each, two tick timers, and four 32-bit general purpose registers.

MVME197LE/D21-1

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Motorola MVME197LE user manual Introduction, General Description

Contents

MVME197LE/D2 MVME197LE Restricted Rights Legend Document Terminology Preface BIT Document Title Motorola Publication Number Related DocumentationPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv General Description Introduction Ote Features Specifications MVME197LE SpecificationsCharacteristics Specifications Cooling Requirements FCC Compliance Equipment Required Support Information Hardware Preparation Unpacking Instructions Hardware Preparation and Installation VMEbus Connector P1 Configuration Switches Switch S1Configuration Switch S1 General Information S1-1 to S1-8 OFF -- All Ones Factory Configuration Installation Instructions Switch S6Connectors MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Controls and Indicators Abort Switch S2Reset Switch S3 Front Panel Indicators DS1-DS6 Memory MapsProcessor Bus Memory Map Processor Bus Memory Map Local Devices Memory Map Address Range Devices Accessed Port Size Detailed I/O Memory Maps 110 BusSwitch Register Memory Map100 108 Memory Maps ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Ecdm CSR Register Memory Map Dcam I2C Register Memory Map Dcam I2C Base Address = $C0 default Offset Operating Instructions Offset VMEchip2 Memory Map Sheet 1 Operating Instructions VMEchip2 Memory Map Sheet 2 Global Access BUS Watchdog Timeout Prescaler Adjust Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Gcsr Base Address = $FFF40100 VMEchip2 Memory Map Sheet 4 Operating Instructions PCCchip2 Memory Map Printer Busy Interrupt Control Register $FFF42034 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer PE Interrupt Control Register $FFF42033 Cirrus Logic CD2400 Memory Map Offsets Size Access Cirrus Logic CD2401 Serial Port Memory MapBase Address Is $FFF45000 Data Bits Address D31 D16 D15 Address Range Description Size Bytes Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map 12. MK48T08 BBRAM, TOD Clock Memory Map 13. Bbram Configuration Area Memory Map 14. TOD Clock Memory MapData Bits Address Function BBRAM, TOD Clock Memory Map 0460000000470476 5000 VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 01-W3869B03A Local Reset Operation Software InitializationMulti-MPU Programming Considerations User’s Manual MVME197LE Functional Description Data Bus StructureMC88110 MPU Functional Description Memory Array Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Mezzanine Address Bus Battery Backup RAM and Clock Flash MemoryOnboard Dram VMEbus Interface InterfacesSerial Port Interface Ethernet Interface Printer Interface Scsi Termination Programmable Tick TimersPeripheral Resources Scsi Interface Interrupt Sources Watchdog TimerProcessor Bus Timeout Local Peripheral Bus Timeout MVME197LE/D2 Functional Description EIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Ring Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Numerics Index IN-2 IN-3 Index