Installation Instructions, Switch S6 | Motorola MVME197LE instruction

2

Hardware Preparation and Installation

Configuration Switch S6: Serial Port 4 Clock Select (S6-1, S6-2)

Serial port 4 can be configured to use clock signals provided by the RTXC4 and TRXC4 signal lines. Switch segments S6-1 and S6-2 on the MVME197LE configures serial port 4 to drive or receive TRXC4 and RTXC4, respectively. Factory configuration is with serial port 4 set to receive both signals (open). The remaining configuration of the clock lines is accomplished by using the Serial Port 4 Clock Configuration Select header on the MVME712M transition module. Refer to the MVME712M Transition Module and P2 Adapter Board User’s Manual for configuration of that header.

Switch S6

O	1	2
N

CLOSED

OPEN

Receive TRXC4

Receive RTXC4

(FACTORY CONFIGURATION)

Switch S6

O	1	2
N

CLOSED

OPEN

Drive TRXC4

Drive RTXCC4

Connectors

The MVME197LE has two 64-position DIN connectors: P1 and P2. Connector P1 rows A, B, C, and connector P2 row B provide the VMEbus interconnection. Connector P2 rows A and C provide the interconnect to the SCSI bus, the serial ports, the Ethernet interface, and the Centronics printer. There is a 249-pin mezzanine connector (J2) with the MC88110 bus interface. This mezzanine connector is for MVME197LE module expansion. There is also a 20-pin general purpose connector (J1) which provides the interconnect to the LEDs and the reset and abort signals. Refer to the SIMVME197LE Single Board Computer Support Information manual for detailed signal descriptions.

Installation Instructions

The following sections discuss installation of the MVME197LE into a VME chassis, and system considerations. Ensure that the BOOT ROM device is installed. Ensure that all switches are configured as desired.

2-6	User’s Manual

Image 26

Motorola MVME197LE user manual Installation Instructions, Switch S6, Connectors

Contents

MVME197LE MVME197LE/D2 Restricted Rights Legend Preface Document Terminology BIT Related Documentation Document Title Motorola Publication NumberPage Page Safety Summary Safety Depends on YOU Contents Appendix a List of Figures Xii List of Tables Xiv Introduction General Description Features Ote Characteristics Specifications SpecificationsMVME197LE Specifications Cooling Requirements Equipment Required FCC Compliance Support Information Unpacking Instructions Hardware Preparation Hardware Preparation and Installation VMEbus Connector P1 Configuration Switch S1 General Information Configuration SwitchesSwitch S1 S1-1 to S1-8 OFF -- All Ones Factory Configuration Connectors Installation InstructionsSwitch S6 MVME197LE Module Installation System Considerations MVME197LE/D2 Hardware Preparation and Installation Reset Switch S3 Controls and IndicatorsAbort Switch S2 Processor Bus Memory Map Front Panel Indicators DS1-DS6Memory Maps Processor Bus Memory Map Address Range Devices Accessed Port Size Local Devices Memory Map Detailed I/O Memory Maps 108 BusSwitch Register Memory Map100 110 Memory Maps Ecdm CSR Register Memory Map ECDM0 ECDM1 ECDM2 ECDM3 ADDR/REGISTER Dcam I2C Base Address = $C0 default Offset Dcam I2C Register Memory Map Operating Instructions VMEchip2 Memory Map Sheet 1 Offset Operating Instructions Global Access BUS Watchdog Timeout Prescaler Adjust VMEchip2 Memory Map Sheet 2 Operating Instructions VMEchip2 Memory Map Sheet 3 Operating Instructions VMEchip2 Memory Map Sheet 4 VMEchip2 Gcsr Base Address = $FFF40100 Operating Instructions PCCchip2 Memory Map Printer PE Interrupt Control Register $FFF42033 Printer Fault Interrupt Control Register $FFF42031Printer SEL Interrupt Control Register $FFF42032 Printer Busy Interrupt Control Register $FFF42034 Base Address Is $FFF45000 Cirrus Logic CD2400 Memory Map Offsets Size AccessCirrus Logic CD2401 Serial Port Memory Map Data Bits Address D31 D16 D15 12. MK48T08 BBRAM, TOD Clock Memory Map Accesses may be 8-bit or 32-bit, but not 16-bit11 C710 Scsi Memory Map Address Range Description Size Bytes Data Bits Address Function 13. Bbram Configuration Area Memory Map14. TOD Clock Memory Map 000000470476 BBRAM, TOD Clock Memory Map0460 01-W3869B03A VMEbus Accesses to the Local Peripheral BusVMEbus Memory Map 5000 Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization User’s Manual MC88110 MPU MVME197LE Functional DescriptionData Bus Structure Functional Description Mezzanine Address Bus Bus Data Bus 256 BusSwitchMC88110 Address Data MUX Address Memory Array Onboard Dram Battery Backup RAM and ClockFlash Memory Serial Port Interface VMEbus InterfaceInterfaces Printer Interface Ethernet Interface Scsi Interface Programmable Tick TimersPeripheral Resources Scsi Termination Local Peripheral Bus Timeout Watchdog TimerProcessor Bus Timeout Interrupt Sources MVME197LE/D2 Functional Description EIA-232-D Interconnections Pin Signal Signal Name and Description Number Mnemonic Table A-1. EIA-232-D Interconnections Ring Indicator RI is sent by the modem to User’s Manual Figure A-1. Middle-of-the-Road EIA-232-D Configuration Figure A-2. Minimum EIA-232-D Connection Index Numerics IN-2 IN-3 Index